DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 94

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 4: WebPACK ISE Design Entry
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Add a new testbench waveform source by right-clicking on “top_sch.sch” and
selecting New Source. Select Test Bench Waveform and name this source
“top_sch_tb.
Click Next> and then associate it with “top.” Click Finish.
Initialize the timing as before, using a Clock High Time and Clock Low Time of
270ns and an Input Setup Time and Output Valid Delay of 50ns. Set the
Initial Length of Test Bench to 100000 ns.
In the waveform diagram, enter the input stimulus as follows:
www.xilinx.com
Figure 4-52: Simulation Timing
Figure 4-51: New Test Bench
Programmable Logic Design
June 12, 2006
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