DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 51

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
HDL Synthesis
ISE Software
R
After (32 x 32 multiplier):
HDL is also ideal for design re-use. You can share your “library” of parts with other
designers at your company, therefore saving and avoiding duplication of effort.
Once we have specified the design in a behavioral description we can convert it into gates
using the process of synthesis. The synthesis tool does the intensive work of figuring out
what gates to use, based on the high-level description file you provide (using schematic
capture, you would have to do this manually.) Because the resulting netlist is vendor and
device family-specific, you must use the appropriate vendor library. Most synthesis tools
support a large range of gate array, FPGA, and CPLD device vendors.
In addition, you can specify optimization criteria that the synthesis tool will take into
account when making the gate-level selections, also called mapping. Some of these options
include: optimizing the complete design for the least number of gates, optimizing a certain
section of the design for fastest speed, using the best gate configuration to minimize power,
and using the FPGA-friendly, register-rich configuration for state machines.
You can easily experiment with different vendors, device families, and optimization
constraints, thus exploring many different solutions instead of just one with the schematic
approach.
To recap, the advantages of high level design and synthesis are many. It is much simpler
and faster to specify your design using HDL, and much easier to make changes to the
design because of the self-documenting nature of the language. You are relieved from the
tedium of selecting and interconnecting at the gate level. You merely select the library and
optimization criteria (e.g., speed, area) and the synthesis tool will determine the results.
You can also try different design alternatives and select the best one for your application. In
fact, there is no real practical alternative for designs exceeding 10,000 gates.
ISE advanced HDL synthesis engines produce optimized results for PLD synthesis, one of
the most essential steps in your design methodology. It takes your conceptual HDL design
definition and generates a logical or physical representation for the targeted silicon device.
A state-of-the-art synthesis engine is required to produce highly optimized results with a
fast compile and turnaround time. To meet this requirement, the synthesis engine must be
tightly integrated with the physical implementation tool and proactively meet design
architecture BEHAVE of MULT is
begin
end BEHAVE;
entity MULT is
port(A,B:in
end MULT;
architecture BEHAVE of MULT is
begin
end BEHAVE;
Y <= A * B;
Y:out
Y <= A * B;
std_logic(31
std_logic(63
www.xilinx.com
downto 0);
downto 0));
HDL Design Process
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