DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 4

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Preface: About This Guide
iv
Conventions
CHAPTER 4: WEBPACK ISE DESIGN ENTRY
CHAPTER 5: IMPLEMENTING CPLD DESIGNS
CHAPTER 6: IMPLEMENTING FPGA DESIGNS
CHAPTER 7: DESIGN REFERENCE BANK
Chapter 4 is a step-by-step approach to your first design. The following pages are intended
to demonstrate the basic PLD design entry implementation process.
Chapter 5 discusses the synthesis and implementation process for CPLDs. The design
targets a CoolRunner-II CPLD.
Chapter 6 discusses teh synthesis and implementation process for FPGAs. The design
targets a Spartan
design is the same design as described in previous chapters, but targets a Spartan-3 FPGA
instead.
Chapter 7 contains a useful list of design examples and applications that will give you a
jump start into your future programmable logic designs. This section also offers pointers
on where to locate and download code and IP cores from the Xilinx website.
Courier font
Courier bold
Helvetica bold
Italic font
Square brackets [ ]
Braces { }
Convention
TM
-3 that is available on the demo board of the Spartan-3 Design Kit. The
Messages, prompts, and
program files that the system
displays
Literal commands that you enter
in a syntactical statement
Commands that you select from
a menu
Keyboard shortcuts
Variables in a syntax statement
for which you must supply
values
References to other manuals
Emphasis in text
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
A list of items from which you
must choose one or more
www.xilinx.com
Meaning or Use
speed grade: - 100
ngdbuild design_name
File → Open
Ctrl+C
ngdbuild design_name
See the Development System
Reference Guide for more
information.
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
ngdbuild [ option_name ]
design_name
lowpwr ={on|off}
Programmable Logic Design
Example
June 12, 2006
R