DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 95
DO-CPLD-DK-G
Manufacturer Part Number
DO-CPLD-DK-G
Description
KIT DESIGN CPLD W/BATT HOLDER
Manufacturer
Xilinx Inc
Series
CoolRunner™- IIr
Type
CPLDr
Specifications of DO-CPLD-DK-G
Contents
Proto Board, Download Cable, Samples, Software
For Use With/related Products
CoolRunner-ll, XC9500XL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1512
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Programmable Logic Design
June 12, 2006
R
Note:
scale as shown above, right click on one of the time intervals (for instance, 2430 ns) and select
Rescale Timing. Set the timing to 10000 ns to get a scale similar to above. You may have to
rescale the timing again to get the scaling shown in
6.
7.
a.
b. Click the RESET cell below CLK cycle 3 to reset it low.
Click File → Save to save the waveform.
With “top_sch_tb.tbw” selected in the Sources window (make sure Behavior
Simulation view is showing),double-click Simulate Behavioral Model in the
Process window.
In the
Set the RESET cell below CLK cycle 1 to a value of “1.”
Figure 4-53
the End Time of 100000 ns will create a more compressed diagram. To
Figure 4-54: Sources and Processes
www.xilinx.com
Figure 4-53: Waveform Diagram
Figure
4-55.
Top-Level Schematic Designs
85
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