DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 87

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Top-Level Schematic Designs
Programmable Logic Design
June 12, 2006
R
Note:
as shown above, right click on one of the time intervals (for instance, 2430 ns) and select Rescale
Timing. Set the timing to 10000 ns to get a scale similar to above. You may have to rescale the
timing again to get the scaling shown in
5.
6.
If the simulation works correctly, you will get a display as shown in
would like to learn how to create schematic top level files, please carry on reading. If you
are not interested in schematic top level files, please go straight to the next chapter of this
handbook.
Sometimes, it’s easier to visualize designs when they have a schematic top level that
instantiates the individual blocks of HDL. The blocks can then be wired together in the
traditional method. For designs in the WebPACK ISE tool, the entire project can be
schematic- based.
This section discusses the method of connecting VHDL modules via the ECS schematic
tool. If you worked through the previous section, you will first need to remove the top
level VHDL file top.vhd from the project. To do this, highlight the file in the sources for
Synthesis/Implementation View, right click and select Remove then click the Yes button
a.
b. Click the RESET cell below CLK cycle 3 to a value of “0”.
Click the save icon.
The “top_tb.tbw” file will now be associated with the top-level VHDL module when
viewing files in the Behavioral Simulation view.
Double-click on Simulate Behavioral Model in the Process window.
In
Set the RESET cell below CLK cycle 1 to a value of “1.”
Figure 4-41
the End Time of 100000 ns will create a more compressed diagram. To scale
www.xilinx.com
Figure 4-41: Waveform Diagram
Figure 4-42: Waveform Window
Figure
4-42.
Top-Level Schematic Designs
Figure
4-42. If you
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