DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 50
DO-CPLD-DK-G
Manufacturer Part Number
DO-CPLD-DK-G
Description
KIT DESIGN CPLD W/BATT HOLDER
Manufacturer
Xilinx Inc
Series
CoolRunner™- IIr
Type
CPLDr
Specifications of DO-CPLD-DK-G
Contents
Proto Board, Download Cable, Samples, Software
For Use With/related Products
CoolRunner-ll, XC9500XL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1512
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Chapter 3: Xilinx Design Software
40
HDL File Change Example
Before (16 x 16 multiplier):
would have to be loaded, positioned on the page, and interconnected, with I/O buffers
added. That would be about three days of work.
The HDL implementation, which is also 6,000 gates, requires eight lines of text and can be
done in three minutes. This file contains all the information necessary to define our 16 x 16
multiplier. So, as a designer, which method would you choose? In addition to the
tremendous time savings, the HDL method is completely vendor-independent. This opens
up tremendous design possibilities for engineers.
To create a 32 x 32 multiplier, you could simply modify the work you’d already done for
the smaller multiplier. For the schematic approach, this would entail making three copies
of the 30 pages, then figuring out where to edit the 90 pages so that they addressed the
larger bus widths. This would probably require four hours of graphical editing. For the
HDL specification, it would be a matter of changing the bus references from 15 to 31 in line
2, and 31 to 63 in line 3. This would probably require about four seconds.
entity MULT is
port(A,B:in std_logic(15 downto 0);
end MULT;
Y:out std_logic(31 downto 0));
Figure 3-3: Design Specification – Multiplier
www.xilinx.com
Programmable Logic Design
June 12, 2006
R
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