DSP56309EVM Freescale Semiconductor, DSP56309EVM Datasheet - Page 251

• Manufacturer Part Number: DSP56309EVM
• Description: KIT EVALUATION FOR XC56309
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of DSP56309EVM

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Description/function: Audio DSPs
• Product: Audio Modules
• For Use With/related Products: DSP56309
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor
DMA Control Registers (DCR5–DCR0)
Reset = $000000
DMA Channel Enable, Bit 23
0 = Disables channel operation
1 = Enables channel operation
Application:
DMA Interrupt Enable, Bit 22
0 = Disables DMA Interrupt
1 = Enables DMA interrupt
23 22 21 20
DE
DMA Transfer Mode, Bits 21–19
DTM[2:0]
DIE
DMA Channel Priority, Bits 18–17
DMA Continuous Mode Enable, Bit 16
0 = Disables continuous mode
1 = Enables continuous mode
000
001
010
011
100
101
110
111
DPR[1:0]
00
01
10
11
DMA Request Source, Bits 15–11
10101 - 11111
DTM[2–0]
00000–00011
00100–01001
01010–01011
01100–01101
01110–01111
10000–10010
request
request
request
DE
request
request
reserved
reserved
DRS[4:0]
10011
10100
Triggered By
Priority level 0 (lowest)
Priority level 1
Priority level 2
Priority level 3 (highest)
19 18 17 16
Figure B-8. DMA Control Registers 5–0 (DCR[5–0])
DPR[1–0] DCON
External (IRQA, IRQB, IRQC, IRQD)
Transfer done from channel 0,1,2,3,4,5
ESSI0 Receive, Transmit Data
ESSI1 Receive, Transmit Data
SCI Receive, Transmit Data
Timer0, Timer1, Timer2
Host Receive Data Full
Host Transmit Data Empty
Reserved
Channel Priority
yes
yes
yes
yes
no
no
DE Cleared
Requesting Device
15 14 13 12 11 10 9
DSP56309 User’s Manual, Rev. 1
block transfer
word transfer
line transfer
block transfer
block transfer
word transfer
Transfer Mode
DRS[4–0]
X:$FFFFD8, X:$FFFFDC, X:$FFFFE0,
X:$FFFFE4, X:$FFFFE8, X:$FFFFEC
1 = Three-Dimensional mode enabled
Three-Dimensional Mode, Bit 10
0 = Three-Dimensional mode disabled
D3D
Three-Dimensional Addressing Modes (D3D=1)
DMA Address Mode, Bits 9–4
Non-Three-Dimensional Addressing Modes (D3D=0)
DAM[2–0] = source
DAM[5:3]
DAM[2:0]
DAM[5:3]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
8
DMA Destination Space, Bits 3–2
2D
2D
2D
2D
No update
Postincrement-by-1
reserved
reserved
DMA Source Space, Bits 1–0
Addressing Mode
DSS[1:0]
2D
2D
2D
2D
No update
Postincrement-by-1
3D
3D
DAM[5–0]
7
DSS[1:0]
00
01
10
11
Addressing Mode
00
01
10
11
6
Date:
Programmer:
5
X Memory Space
Y Memory Space
P Memory Space
Reserved
DAM[5–3] = Destination
X Memory Space
Y Memory Space
P Memory Space
Reserved
DMA Destination Memory
B
B
B
B
A
A
4
Counter
Mode
DMA Source Memory
DOR0
DOR1
DOR2
DOR3
None
DOR0: DOR1
DOR2: DOR3
None
DDS[1–0]
3
Read/Write
Offset Selection
Programming Sheets
DMA
DOR0
DOR1
DOR2
DOR3
None
None
2
Offset Register
Selection
Sheet 1 of 1
DSS[1–0]
1
0
B-17