mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet

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mc56f8335

Manufacturer Part Number
mc56f8335
Description
16-bit Digital Signal Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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56F8335/56F8135
Data Sheet
Preliminary Technical Data
MC56F8335
Rev. 5
01/2007
56F8300
16-bit Digital Signal Controller
freescale.com

Related parts for mc56f8335

mc56f8335 Summary of contents

Page 1

... Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controller MC56F8335 Rev. 5 01/2007 freescale.com ...

Page 2

Version History Rev. 0 Initial Release Rev. 1 Deleted RSTO from Pin Group 2 (listed after Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in Table 10-4. Added RoHS-compliance and “pb-free” language to back cover. Rev. 2 Added information/corrected ...

Page 3

General Description Note: Features in italics are NOT available in the 56F8135 device. • MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 64KB Program Flash • 4KB Program ...

Page 4

Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56F8335/56F8135 Features . . . . . . . . . . ...

Page 5

Part 1 Overview 1.1 56F8335/56F8135 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • ...

Page 6

Memory Note: Features in italics are NOT available in the 56F8135 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection feature • On-chip memory, including a low-cost, high-volume ...

Page 7

General Purpose I/O (GPIO) pins; 28 pins dedicated to GPIO • External reset input pin for hardware reset • External reset output pin for system reset • Integrated low-voltage interrupt module • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, ...

Page 8

Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature ...

Page 9

DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters ...

Page 10

JTAG / EOnCE 56800E CHIP TAP Controller TAP Linking Module External JTAG Port cdbr_m[31:0] xdb2_m[15:0 NOT available on the 56F8135 device. * EMI not functional in this package; since only part of the address/data bus is bonded out, use ...

Page 11

CLKGEN (OSC / PLL) Timer A 4 Quadrature Decoder 0 4 Timer D Timer B 4 Quadrature Decoder NOT available on the 56F8135 device. Freescale Semiconductor Preliminary To/From IPBus Bridge SPI1 GPIOA GPIOB GPIOC GPIOD GPIOE ...

Page 12

... Secondary Data Memory Interface Peripheral Interface Bus are required for a complete description and proper design with the Freescale Literature Distribution Table 1-3 Chip Documentation Description 56F8335 Technical Data, Rev. 5 Centers, or online at Order Number DSP56800ERM MC56F8300UM MC56F83xxBLUM MC56F8335 MC56F8335E MC56F8135E Freescale Semiconductor Preliminary ...

Page 13

Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) ...

Page 14

Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8335 and 56F8135 are organized into functional groups, as detailed in Table 2-2 and as illustrated in present on a pin. Table 2-1 Functional Group Pin Allocations ...

Page 15

Power V V Power DDA_ADC V Power DDA_OSC_PLL Ground V Ground SSA_ADC OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL EXTAL and XTAL Clock CLKO A8 - A13 (GPIOA0 - 5) * ...

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Power Power V Power DDA_OSC_PLL Ground Ground Other V CAP Supply V PP Ports CLKMODE PLL and Clock A8 - A13 (GPIOA0 - 5) * External Address GPIOB0-4 (A16 - 20) Bus or GPIO D7 - D10 (GPIOF0 - 3) ...

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Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. EMI is not functional in this package; since only part of the address/data bus is bonded out, use as ...

Page 18

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name V 95 Supply SSA_ADC OCR_DIS 71 Input Supply CAP V 2 122 CAP CAP CAP ...

Page 19

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name CLKO 6 Output A8 15 Output (GPIOA0) Schmitt Input Output (GPIOA1) A10 17 (GPIOA2) A11 18 (GPIOA3) A12 19 (GPIOA4) A13 20 ...

Page 20

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name GPIOB4 31 Schmitt Input/ Output (A20) Output (prescaler_ Output clock Input/ Output (GPIOF0) Input/ Output D8 23 (GPIOF1 (GPIOF2) D10 ...

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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name GPIOD0 42 Input/ Output (CS2) Output GPIOD1 43 (CS3) GPIOD2 44 (CS4) GPIOD3 45 (CS5) GPIOD4 46 (CS6) GPIOD5 47 (CS7) TXD0 7 Output ...

Page 22

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name RXD1 41 Input (GPIOD7) Input/ Output TCK 115 Schmitt Input TMS 116 Schmitt Input TDI 117 Schmitt Input TDO 118 Output 22 State During ...

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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name TRST 114 Schmitt Input PHASEA0 127 Schmitt Input (TA0) Schmitt Input/ Output (GPIOC4) Schmitt Input/ Output PHASEB0 128 Schmitt Input (TA1) Schmitt Input/ Output ...

Page 24

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name INDEX0 1 Schmitt Input (TA2) Schmitt Input/ Output (GPIOC6) Schmitt Input/ Output HOME0 2 Schmitt Input (TA3) Schmitt Input/ Output (GPIOC7) Schmitt Input/ Output ...

Page 25

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name MOSI0 126 Input/ Output (GPIOE5) Input/ Output MISO0 125 Input/ Output (GPIOE6) Input/ Output SS0 123 Input (GPIOE7) Input/ Output Freescale Semiconductor Preliminary State ...

Page 26

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name PHASEA1 9 Schmitt Input (TB0) Schmitt Input/ Output (SCLK1) Schmitt Input/ Output (GPIOC0) Schmitt Input/ Output PHASEB1 10 Schmitt Input (TB1) Schmitt Input/ Output ...

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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name INDEX1 11 Schmitt Input (TB2) Schmitt Input/ Output Schmitt (MISO1) Input/ Output Schmitt (GPIOC2) Input/ Output HOME1 12 Schmitt Input (TB3) Schmitt Input/ Output ...

Page 28

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name PWMA0 58 Output PWMA1 60 PWMA2 61 PWMA3 63 PWMA4 64 PWMA5 66 ISA0 104 Schmitt Input (GPIOC8) Schmitt Input/ ISA1 105 Output (GPIOC9) ...

Page 29

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name ISB0 48 Schmitt Input (GPIOD10) Schmitt Input/ ISB1 50 Output (GPIOD11) ISB2 51 (GPIOD12) FAULTB0 54 Schmitt Input FAULTB1 55 FAULTB2 56 FAULTB3 57 ...

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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name ANB0 96 Input ANB1 97 ANB2 98 ANB3 99 ANB4 100 Input ANB5 101 ANB6 102 ANB7 103 TEMP_ 88 Output SENSE CAN_RX 121 ...

Page 31

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name TD0 107 Schmitt Input/ Output (GPIOE10) Schmitt TD1 108 Input/ (GPIOE11) Output TD2 109 (GPIOE12) TD3 110 (GPIOE13) IRQA 52 Schmitt Input IRQB 53 ...

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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name EXTBOOT Internal Schmitt Ground Input EMI_MODE Internal Schmitt Ground Input 32 State During Signal Description Reset Input, External Boot — This input is tied ...

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Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. specific OCCS ...

Page 34

Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL R Z CLKMODE = 0 CL1 Figure 3-2 Connecting to a Crystal Oscillator Note: The OCCS_COHL bit must be set ...

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Figure 3-4 Connecting an External Clock Signal Register 3.3 Registers When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions without the internal Relaxation Oscillator, since the 56F8335/56F8135 devices do NOT ...

Page 36

Table 4-1 Chip Memory Configurations On-Chip Memory 56F8335 Data Flash 8KB Program RAM 4KB Data RAM 8KB Program Boot Flash 8KB 4.2 Program Map The Program memory map is located in Operating Mode Register (OMR) control the Program memory map. ...

Page 37

Setting this bit can cause unpredictable results and is not recommended, since the EMI is not functional in this package. Table 4-4 shows the memory map options of the 56F8335/56F8135. The two right columns cannot be used, since the ...

Page 38

All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base ...

Page 39

Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level FM 24 0-2 FLEXCAN 26 0-2 FLEXCAN 27 0-2 FLEXCAN 28 0-2 FLEXCAN 29 0-2 GPIOF 30 0-2 GPIOE 31 0-2 GPIOD 32 0-2 GPIOC 33 0-2 GPIOB 34 ...

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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level DEC1 47 0-2 DEC1 48 0-2 DEC0 49 0-2 DEC0 50 0-2 TMRD 52 0-2 TMRD 53 0-2 TMRD 54 0-2 TMRD 55 0-2 TMRC 56 0-2 TMRC 57 ...

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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level PWMA 80 0-2 core Two words are allocated for each entry in the vector table. This does not allow the full address range to be ...

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Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by ...

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Flash Size Data Flash Data Flash Boot Flash Please see the 56F8300 Peripheral User Manual for additional Flash information. 4.6 EOnCE Memory Map Address Register Acronym X:$FF FF8A OESCR X:$FF FF8E OBCNTR X:$FF FF90 OBMSK (32 bits) X:$FF FF91 — ...

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Table 4-8 EOnCE Memory Map (Continued) Address Register Acronym X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFF OTX1 / ORX1 4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. ...

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Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral GPIO Port C GPIO Port D GPIO Port E GPIO Port F SIM Power Supervisor FM FlexCAN Freescale Semiconductor Preliminary Prefix Base Address GPIOC X:$00 F310 GPIOD X:$00 F320 ...

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Table 4-10 External Memory Integration Registers Address Map Register Address Acronym Offset CSBAR 0 $0 Chip Select Base Address Register 0 CSBAR 1 $1 Chip Select Base Address Register 1 CSBAR 2 $2 Chip Select Base Address Register 2 CSBAR ...

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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA0_CNTR TMRA0_CTRL TMRA0_SCR TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR Freescale ...

Page 48

Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSCR Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in the 56F8135 device ...

Page 49

Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8135 device Register Acronym TMRB1_CTRL TMRB1_SCR TMRB1_CMPLD1 TMRB1_CMPLD2 TMRB1_COMSCR TMRB2_CMP1 TMRB2_CMP2 TMRB2_CAP TMRB2_LOAD TMRB2_HOLD TMRB2_CNTR TMRB2_CTRL TMRB2_SCR TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP ...

Page 50

Table 4-13 Quad Timer C Registers Address Map Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR ...

Page 51

Table 4-13 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Table 4-14 Quad Timer D Registers Address Map Quad Timer D is NOT available in the ...

Page 52

Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8135 device Register Acronym TMRD1_CAP TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR TMRD2_CMPLD1 TMRD2_CMPLD2 ...

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Table 4-15 Pulse Width Modulator A Registers Address Map PWMA is NOT available in the 56F8135 device Register Acronym PWMA_PMCTL PWMA_PMFCTL PWMA_PMFSA PWMA_PMOUT PWMA_PMCNT PWMA_PWMCM PWMA_PWMVAL0 PWMA_PWMVAL1 PWMA_PWMVAL2 PWMA_PWMVAL3 PWMA_PWMVAL4 PWMA_PWMVAL5 PWMA_PMDEADTM PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Table 4-16 ...

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Table 4-16 Pulse Width Modulator B Registers Address Map (Continued) Register Acronym PWMB_PWMVAL2 PWMB_PWMVAL3 PWMB_PWMVAL4 PWMB_PWMVAL5 PWMB_PMDEADTM PWMB_PMDISMAP1 PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Table 4-17 Quadrature Decoder 0 Registers Address Map Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV DEC0_REVH ...

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Table 4-18 Quadrature Decoder 1 Registers Address Map Quadrature Decoder 1 is NOT available in the 56F8135 device Register Acronym DEC1_DECCR DEC1_FIR DEC1_WTR DEC1_POSD DEC1_POSDH DEC1_REV DEC1_REVH DEC1_UPOS DEC1_LPOS DEC1_UPOSH DEC1_LPOSH DEC1_UIR DEC1_LIR DEC1_IMR Table 4-19 Interrupt Control Registers Address ...

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Table 4-19 Interrupt Control Registers Address Map (Continued) Register Acronym VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 IRQP 2 IRQP 3 IRQP 4 IRQP 5 ICTL Table 4-20 Analog-to-Digital Converter Registers Address Map Register Acronym ADCA_CR1 ...

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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_RSLT 5 ADCA_RSLT 6 ADCA_RSLT 7 ADCA_LLMT 0 ADCA_LLMT 1 ADCA_LLMT 2 ADCA_LLMT 3 ADCA_LLMT 4 ADCA_LLMT 5 ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ...

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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_POWER ADCA_CAL Table 4-21 Analog-to-Digital Converter Registers Address Map Register Acronym ADCB_CR1 ADCB_CR2 ADCB_ZCC ADCB_LST 1 ADCB_LST 2 ADCB_SDIS ADCB_STAT ADCB_LSTAT ADCB_ZCSTAT ADCB_RSLT 0 ADCB_RSLT 1 ADCB_RSLT 2 ADCB_RSLT 3 ...

Page 59

Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCB_HLMT 2 ADCB_HLMT 3 ADCB_HLMT 4 ADCB_HLMT 5 ADCB_HLMT 6 ADCB_HLMT 7 ADCB_OFS 0 ADCB_OFS 1 ADCB_OFS 2 ADCB_OFS 3 ADCB_OFS 4 ADCB_OFS 5 ADCB_OFS 6 ADCB_OFS 7 ADCB_POWER ADCB_CAL ...

Page 60

Table 4-23 Serial Communication Interface 0 Registers Address Map (Continued) Register Acronym SCI0_SCICR SCI0_SCISR SCI0_SCIDR Table 4-24 Serial Communication Interface 1 Registers Address Map Register Acronym SCI1_SCIBR SCI1_SCICR SCI1_SCISR SCI1_SCIDR Table 4-25 Serial Peripheral Interface 0 Registers Address Map Register ...

Page 61

Table 4-27 Computer Operating Properly Registers Address Map Register Acronym COPCTL COPTO COPCTR Table 4-28 Clock Generation Module Registers Address Map Register Acronym PLLCR PLLDB PLLSR SHUTDOWN OSCTL Table 4-29 GPIOA Registers Address Map Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER ...

Page 62

Table 4-30 GPIOB Registers Address Map Register Acronym GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Table 4-31 GPIOC Registers Address Map Register Acronym GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA 62 (GPIOB_BASE ...

Page 63

Table 4-32 GPIOD Registers Address Map Register Acronym Address Offset GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA Table 4-33 GPIOE Registers Address Map Register Acronym Address Offset GPIOE_PUR GPIOE_DR GPIOE_DDR GPIOE_PER GPIOE_IAR GPIOE_IENR GPIOE_IPOLR GPIOE_IPR GPIOE_IESR ...

Page 64

Table 4-34 GPIOF Registers Address Map Register Acronym GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR GPIOF_PPMODE GPIOF_RAWDATA Table 4-35 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS ...

Page 65

Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Table 4-37 Flash Module Registers Address Map Register Acronym FMCLKD FMMCR FMSECH FMSECL FMPROT FMPROTB FMUSTAT FMCMD FMOPT 0 FMOPT 1 FMOPT 2 Freescale Semiconductor Preliminary (LVI_BASE = $00 ...

Page 66

Table 4-38 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8135 device Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR FCMAXMB FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH ...

Page 67

Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8135 device Register Acronym FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA ...

Page 68

Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8135 device Register Acronym FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA ...

Page 69

Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8135 device Register Acronym FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA ...

Page 70

Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8135 device Register Acronym FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA 70 (FC_BASE = $00 F800) ...

Page 71

Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application can be used to load a user application into the Program and Data Flash(NOT available in the ...

Page 72

Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition 1 ...

Page 73

Block Diagram Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...

Page 74

Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has ...

Page 75

Add. Register Offset Name IPR0 BKPT_U0 IPL IPR1 IPR2 FMCBE IPL FMCC IPL W R GPIOD $3 IPR3 IPL W R SPI0_RCV SPI1_XMIT $4 ...

Page 76

Figure 5-2 ITCN Register Map Summary 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $ Read 0 0 BKPT_U0IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field ...

Page 77

Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the ...

Page 78

Interrupt Priority Register 2 (IPR2) Base + $ Read FMCBE IPL FMCC IPL Write RESET Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level ...

Page 79

Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ ...

Page 80

GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) ...

Page 81

FlexCAN Error Interrupt Priority Level (FCERR IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled ...

Page 82

SPI 1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...

Page 83

IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $5 15 ...

Page 84

IRQ is priority level 1 • IRQ is priority level 2 5.6.6.4 SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. ...

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Interrupt Priority Register 6 (IPR6) Base + $ Read TMRC0 TMRD3 IPL Write RESET Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 ...

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IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.7.5 Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)— Bits 7–6 This field is used ...

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Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...

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IRQ is priority level 2 5.6.8.6 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. ...

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SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...

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IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2 This field is used to ...

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IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—Bits 11–10 ...

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ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...

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Fast Interrupt 0 Match Register (FIM0) Base + $ Read Write RESET Figure 5-14 Fast Interrupt 0 Match Register (FIM0) 5.6.12.1 Reserved—Bits 15–7 This bit field is reserved or not ...

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Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in ...

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Reserved—Bits 15–5 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 The upper five bits of the vector address are ...

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IRQ Pending 2 Register (IRQP2) Base + $ Read Write RESET Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the ...

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No IRQ pending for this vector number 5.6.23 IRQ Pending 5 Register (IRQP5) Base + $ Read Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits ...

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ITCN Control Register (ICTL) Base + $ Read INT IPIC Write RESET Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the ...

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IRQB State Pin (IRQB STATE)—Bit 3 This read-only bit reflects the state of the external IRQB pin. 5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2 This read-only bit reflects the state of the external IRQA pin. 5.6.30.8 IRQB Edge Pin ...

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Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system ...

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Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and ...

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Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Address Acronym Base + $0 SIM_CONTROL Base + $1 SIM_RSTSTS Base + $2 SIM_SCR0 Base + $3 SIM_SCR1 Base + $4 SIM_SCR2 Base + $5 SIM_SCR3 Base ...

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Add. Register Offset Name SIM_ $0 CONTROL SIM_ $1 RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ ...

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Stop Disable (STOP_DISABLE)—Bits 3–2 • Stop mode will be entered when the 56800E core executes a STOP instruction • The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be reprogrammed in ...

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Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET pin being asserted low. 6.5.2.5 Power-On Reset (POR)—Bit 2 When 1, the POR bit indicates a Power-On Reset occurred some ...

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Base + $ Read Write RESET Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID) 6.5.6 SIM Pull-up Disable Register (SIM_PUDR) Most of the pins on the chip have on-chip pull-up ...

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XBOOT—Bit 9 This bit controls the pull-up resistors on the EXTBOOT pin. Note: In this package, this input pin is double-bonded with the adjacent V changed order to reduce power consumption. 6.5.6.8 PWMB—Bit 8 This ...

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Reserved—Bits 15–10 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.7.2 Alternate GPIO_B Peripheral Function for A23 (A23)—Bit 9 • Peripheral output function of GPIOB[7] is ...

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Reserved for factory test—SYS_CLK_DIV2 • 01111 = Reserved for factory test—SYS_CLK_D • 10000 = ADCA clock • 10001 = ADCB clock 6.5.8 GPIO Peripheral Select Register (SIM_GPS) The GPIO Peripheral Select Register can be used to multiplex ...

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Table 6-2 Control of Pads Using SIM_GPS Control Pin Function Quad Timer Input / 1 Quad Decoder 2 Input Quad Timer 1 Output / Quad 3 Decoder Input SPI input 1 SPI output 1 1. This applies to the four ...

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PHASEB1/TB1 (default) • MOSI1 6.5.8.5 GPIOC0 (C0)—Bit 0 This bit selects the alternate function for GPIOC0. • PHASEA1/TB0 (default) • SCLK1 6.5.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable ...

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Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 Decoder 0 Enable (DEC0)—Bit 10 Each bit controls clocks to the indicated peripheral. • Clocks are ...

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Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral. • ...

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I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt. Note: The default value of this register set points to the EOnCE registers. ...

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Power-Down Modes Overview The 56F8335/56F8135 operate in one of three power-down modes, as shown in Table 6-3 Clock Operation in Power-Down Modes Mode Core Clocks Run Active Wait Core and memory clocks disabled Stop System clocks continue to be ...

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Stop and Wait Mode Disable Function Permanent Disable Reprogrammable Disable Clock Select Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop ...

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Part 7 Security Features The 56F8335/56F8135 offer security features intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized ...

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Flash Lockout Recovery If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling Flash security. Access ...

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Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[ Using the ...

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Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information in the 56F8300 Peripheral User ...

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Table 8-1 56F8335 GPIO Ports Configuration Available Port GPIO Port Pins in Width 56F8335 Table 8-2 56F8135 GPIO Ports Configuration Available Port GPIO Port Pins in Width 56F8135 ...

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Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8335 / 56F8135 Pins in italics are NOT available in the 56F8135 device GPIO Port GPIO Bit GPIOA GPIOB 122 Reset Function 0 Peripheral 1 Peripheral ...

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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8335 / 56F8135 Pins in italics are NOT available in the 56F8135 device GPIO Port GPIO Bit GPIOC GPIOD Freescale Semiconductor Preliminary Reset Function 0 ...

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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8335 / 56F8135 Pins in italics are NOT available in the 56F8135 device GPIO Port GPIO Bit GPIOE 124 Reset Function 0 Peripheral 1 Peripheral ...

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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8335 / 56F8135 Pins in italics are NOT available in the 56F8135 device GPIO Port GPIO Bit GPIOF 1. Not useful in reset configuration in ...

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Part 10 Specifications 10.1 General Characteristics The 56F8335/56F8135 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up ...

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Table 10-1 Absolute Maximum Ratings (Continued) Characteristic Input Voltage (analog) Output Voltage Output Voltage (open drain) Ambient Temperature (Automotive) Ambient Temperature (Industrial) Junction Temperature (Automotive) Junction Temperature (Industrial) Storage Temperature (Automotive) Storage Temperature (Industrial corresponding GPIO pin is ...

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Table 10-2 ElectroStatic Discharge (ESD) Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection Junction ...

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TJ = Junction Temperature TA = Ambient Temperature Note: The 56F8135 device is guaranteed to 40MHz and specified to meet Industrial requirements only; CAN is NOT available on the 56F8135 device 0V, V REFLO Characteristic Supply voltage ...

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DC Electrical Characteristics Note: The 56F8135 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8135 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Characteristic Symbol Output High Voltage V OH ...

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Table 10-6 Power-On Reset Low Voltage Parameters Characteristic POR Trip Point 1 LVI, 2.5 volt Supply, trip point 2 LVI, 3.3 volt supply, trip point Bias Current 1. When V drops below V DD_CORE 2. When V drops below V ...

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Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) I Mode DD_Core RUN1_MAC 150mA Wait3 86mA Stop1 800μA Stop2 100μ Output Switching Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200mA ...

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Characteristics PLL Start-up time Resonator Start-up time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8135 device. Table 10-11 Temperature Sense Parametrics Characteristics 1 Slope (Gain) ...

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AC Electrical Characteristics Tests are conducted using the input levels specified in propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in ...

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External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements Characteristic Frequency of operation (external clock driver) 3 Clock Pulse Width 4 External clock input rise time 5 External clock input fall time 1. Parameters listed are guaranteed ...

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Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Bias Current, high-drive mode Bias Current, low-drive mode ...

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RESET t RAZ A0–A15, D0–D15 Figure 10-4 Asynchronous Reset Timing IRQA, IRQB Figure 10-5 External Interrupt Timing (Negative Edge-Sensitive) A0–A15 t IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 10-6 External Level-Sensitive Interrupt Timing ...

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IW IRQA A0–A15 Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing 10.9 Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master ...

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Characteristic Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-9 SPI ...

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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 1) 140 SS is held High on master ...

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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-11 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...

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Quad Timer Timing Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period 1. In the formulas listed the clock cycle. For 60MHz operation 16.67ns. 2. ...

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Phase A (Input) Phase B (Input) Figure 10-14 Quadrature Decoder Timing 10.12 Serial Communication Interface (SCI) Timing Characteristic Symbol 2 Baud Rate 3 RXD RXD Pulse Width 4 TXD TXD Pulse Width 1. Parameters listed are guaranteed by design. 2. ...

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Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8135 device. Characteristic Baud Rate Bus Wake Up detection 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin (Input) Figure 10-17 Bus Wake Up ...

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TCK (Input – Figure 10-18 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-19 Test Access Port Timing Diagram TRST ...

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Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion range ADC channel power-up time ADC reference circuit power-up time Conversion time Sample time Input capacitance 5 Input injection current , ...

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Table 10-23 ADC Parameters (Continued) Characteristic Signal-to-noise plus distortion ratio Total Harmonic Distortion Spurious Free Dynamic Range 8 Effective Number Of Bits 1. INL measured from V = .1V in REFH 10% to 90% Input Signal Range 2. LSB = ...

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Figure 10-21 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken ...

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S3 is closed/open. When S1/S2 are closed & open, one input of the sample and hold circuit moves REFH switches are flipped, the charge on C1 and C2 are ...

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C, the internal [dynamic component], is classic C*V 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly ...

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Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. in the IO cells as a function of capacitive load. In these cases: Total Power = ...

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Part 11 Packaging 11.1 56F8335 Package and Pin-Out Information This section contains package and pin-out information for the 56F8335. This device comes in a 128-pin Low-profile Quad Flat Pack (LQFP). Figure 11-3 shows the mechanical parameters for this package, and ...

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INDEX0 HOME0 PIN DD_IO CLKO TXD0 RXD0 PHASEA1 PHASEB1 INDEX1 HOME1 V 4 CAP V DD_IO GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 V SS GPIOF0 GPIOF1 GPIOF2 V DD_IO GPIOF3 GPIOB0 GPIOB1 GPIOB2 ...

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Table 11-1 56F8335 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No DD_IO CLKO 7 TXD0 8 RXD0 9 PHASEA1 10 PHASEB1 11 INDEX1 12 ...

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Table 11-1 56F8335 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. 31 GPIOB4 32 PWMB0 11.2 56F8135 Package and Pin-Out Information This section contains package and pin-out information for the 56F8135. This device comes ...

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INDEX0 HOME0 PIN DD_IO CLKO TXD0 RXD0 SCLK1 MOSI1 MISO1 SS1 V 4 CAP V DD_IO GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 V SS GPIOF0 GPIOF1 GPIOF2 V DD_IO GPIOF3 GPIOB0 GPIOB1 GPIOB2 ...

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Table 11-2 56F8135 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No DD_IO CLKO 7 TXD0 8 RXD0 9 SCLK1 10 MOSI1 11 MISO1 12 ...

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Table 11-2 56F8135 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. 28 GPIOB1 29 GPIOB2 30 GPIOB3 31 GPIOB4 32 PWMB0 158 Signal Name Pin No ...

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NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF ...

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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC56F8335 Rev. 5 01/2007 ...

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