PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 118
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 118 of 586
- Download datasheet (6Mb)
location just programmed should be verified and
PIC18F47J53 FAMILY
7.5.3
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.4
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
TABLE 7-2:
DS39964B-page 118
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.
Name
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Program Memory Control Register 2 (not a physical register)
GIE/GIEH
Bit 7
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
—
—
PEIE/GIEL
Bit 6
—
—
WPROG
TMR0IE
bit 21
Bit 5
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Preliminary
INT0IE
FREE
Bit 4
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset, or a WDT time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
7.6
See Section 28.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
WRERR
RBIE
Bit 3
Flash Program Operation During
Code Protection
TMR0IF
WREN
Bit 2
2010 Microchip Technology Inc.
INT0IF
Bit 1
WR
RBIF
Bit 0
—
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