PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 391
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 391 of 586
- Download datasheet (6Mb)
23.4.1.3
When the BD and its buffer are owned by the SIE, most
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 23-6. Once UOWN
is set, any data or control settings previously written
there by the user will be overwritten with data from the
SIE.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID) which is stored in
BDnSTAT<5:2>. The transfer count in the correspond-
ing BDnCNT register is updated. Values that overflow
the 8-bit register carry over to the two most significant
digits of the count, stored in BDnSTAT<1:0>.
23.4.2
The byte count represents the total number of bytes
that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.
REGISTER 23-6:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-2
bit 1-0
UOWN
R/W-x
BD BYTE COUNT
BDnSTAT Register (SIE Mode)
UOWN: USB Own bit
1 = The SIE owns the BD and its corresponding buffer
Reserved: Not written by the SIE
PID<3:0>: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
BC<9:8>: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.
r-x
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), SIE MODE (DATA RETURNED BY THE SIE TO THE MCU)
r
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R/W-x
PID3
R/W-x
PID2
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F47J53 FAMILY
R/W-x
The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
register. The upper two bits reside in BDnSTAT<1:0>.
This represents a valid byte range of 0 to 1023.
23.4.3
The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
No mechanism is available in hardware to validate the
BD address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint’s buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
unexpected
applications, the user may want to consider the
inclusion of software-based address validation in their
code.
PID1
BD ADDRESS VALIDATION
R/W-x
PID0
results.
When
x = Bit is unknown
R/W-x
BC9
developing
DS39964B-page 391
R/W-x
BC8
bit 0
USB
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