PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 386
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 386 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
23.2.4
Each of the 16 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’
represents the endpoint number). Each register has an
identical complement of control bits.
Register 23-4 provides the prototype.
The EPHSHK bit (UEPn<4>) controls handshaking for
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using
isochronous endpoints.
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint. Clearing this bit enables SETUP transac-
tions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
REGISTER 23-4:
DS39964B-page 386
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
USB ENDPOINT CONTROL
Unimplemented: Read as ‘0’
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers are allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers are also allowed
EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output is enabled
0 = Endpoint n output is disabled
EPINEN: Endpoint Input Enable bit
1 = Endpoint n input is enabled
0 = Endpoint n input is disabled
EPSTALL: Endpoint Stall Indicator bit
1 = Endpoint n has issued one or more STALL packets
0 = Endpoint n has not issued any STALL packets
U-0
—
UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
(BANKED F26h-F35h)
W = Writable bit
‘1’ = Bit is set
U-0
—
EPHSHK
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EPCONDIS
R/W-0
transactions. For Endpoint 0, this bit should always be
cleared
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (UEPn<2>) is used to enable or
disable USB OUT transactions from the host. Setting
this bit enables OUT transactions. Similarly, the
EPINEN bit (UEPn<1>) enables or disables USB IN
transactions from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that end-
point pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE is
reset.
since
EPOUTEN
R/W-0
the
USB
2010 Microchip Technology Inc.
x = Bit is unknown
EPINEN
R/W-0
specifications
EPSTALL
R/W-0
identify
bit 0
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