PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 159
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 159 of 586
- Download datasheet (6Mb)
TABLE 10-11: PORTE I/O SUMMARY
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
2010 Microchip Technology Inc.
PORTE
LATE
TRISE
ANCON0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/AN5/
PMRD
RE1/AN6/
PMWR
RE2/AN7/
PMCS
V
V
AV
V
V
V
AV
AV
V
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
SS
SS
DD
DD
DDCORE
USB
Note:
SS
DD
DD
Name
1
2
1
2
(1)
1
1
2
Pin
(1)
(1)
/V
These registers and/or bits are not available in 28-pin devices (PIC18F26J53, PIC18F27J53,
PIC18LF26J53 and PIC18LF26J53).
I = Input; O = Output; P = Power
bit 7 RDPU: PORTD Pull-up Enable bit
0 = All PORTD pull-ups are disabled
1 = PORTD pull-ups are enabled for any input pad
bit 6 REPU: PORTE Pull-up Enable bit
0 = All PORTE pull-ups are disabled
1 = PORTE pull-ups are enabled for any input pad
CAP
PCFG7
RDPU
Bit 7
Function
V
—
—
PMWR
PMRD
PMCS
DDCORE
V
RE0
AN5
RE1
AN6
RE2
AN7
—
—
—
—
—
CAP
(1)
PCFG6
Setting
REPU
Bit 6
TRIS
—
—
—
—
—
—
—
—
—
1
0
1
1
0
1
0
1
1
0
1
0
1
0
(1)
I/O
—
O
O
O
O
O
O
P
P
P
P
P
P
P
PCFG5
I
I
I
I
I
I
I
I
Bit 5
—
—
—
ST/TTL Parallel Master Port (io_rd_in).
ST/TTL Parallel Master Port (io_wr_in).
Type
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
—
—
—
—
—
—
—
(1)
Preliminary
PORTE<0> data input; disabled when analog input is enabled.
LATE<0> data output; not affected by analog input.
A/D Input Channel 5; default input configuration on POR.
Parallel Master Port read strobe.
PORTE<1> data input; disabled when analog input is enabled.
LATE<1> data output; not affected by analog input.
A/D Input Channel 6; default input configuration on POR.
Parallel Master Port write strobe.
PORTE<2> data input; disabled when analog input is enabled.
LATE<2> data output; not affected by an analog input.
A/D Input Channel 7; default input configuration on POR.
Parallel Master Port byte enable.
Ground reference for logic and I/O pins.
Ground reference for analog modules.
Positive supply for peripheral digital logic and I/O pins.
Positive supply for microcontroller core logic (regulator disabled).
External filter capacitor connection (regulator enabled).
Positive supply for analog modules.
USB voltage input pin.
PCFG4
Bit 4
—
—
—
PIC18F47J53 FAMILY
PCFG3
Bit 3
—
—
—
Description
TRISE2
PCFG2
LATE2
Bit 2
RE2
TRISE1
PCFG1
LATE1
Bit 1
RE1
DS39964B-page 159
TRISE0
PCFG0
LATE0
Bit 0
RE0
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