PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 312
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 312 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
REGISTER 20-6:
DS39964B-page 312
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
2:
3:
4:
When enabled, the SDAx and SCLx pins must be configured as inputs.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the
SSPxMSK register.
This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is ‘1’).
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPxBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0 = Disables the serial port and configures these pins as I/O port pins
CKP: SCKx Release Control bit
In Slave mode:
1 = Releases clock
0 = Holds clock low (clock stretch); used to ensure data setup time
In Master mode:
Unused in this mode.
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1001 = Load the SSPxMSK register at the SSPxADD SFR address
1000 = I
0111 = I
0110 = I
SSPOV
R/W-0
transmission to be started (must be cleared in software)
software)
software)
SSPxCON1: MSSPx CONTROL REGISTER 1 (I
2
2
2
2
2
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Firmware Controlled Master mode (slave Idle)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
(1)
R/W-0
CKP
Preliminary
OSC
/(4 * (SSPxADD + 1))
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
(1)
(2)
2
C MODE) (1, ACCESS FC6h; 2, F73h)
SSPM2
R/W-0
(2)
2
(3,4)
C conditions were not valid for a
(2)
2010 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
(2)
SSPM0
R/W-0
bit 0
(2)
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