PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 375
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 375 of 586
- Download datasheet (6Mb)
22.2
The ADCON1 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT<2:0> bits
(ADCON1<5:3>) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
22.3
The A/D conversion time per bit is defined as T
A/D conversion requires 11 T
and 13 T
A/D conversion clock is software selectable.
There are seven possible options for T
• 2 T
• 4 T
• 8 T
• 16 T
• 32 T
• 64 T
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(T
minimum T
more information).
Table 22-1 provides the resultant T
from the device operating frequencies and the A/D
clock source selected.
2010 Microchip Technology Inc.
AD
) must be as short as possible but greater than the
OSC
OSC
OSC
OSC
OSC
OSC
Selecting and Configuring
Automatic Acquisition Time
Selecting the A/D Conversion
Clock
AD
AD
per 12-bit conversion. The source of the
(see parameter 130 in Table 31-30 for
AD
per 10-bit conversion
AD
AD
times derived
:
AD
. The
Preliminary
PIC18F47J53 FAMILY
TABLE 22-1:
22.4
The ANCON0, ANCON1 and TRISA registers control
the operation of the A/D port pins. The port pins needed
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (V
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
Operation ADCS<2:0> 10-Bit Mode 12-Bit Mode
Note 1:
16 T
32 T
64 T
2 T
4 T
8 T
RC
Note 1: When reading the PORT register, all pins
AD Clock Source
OSC
OSC
OSC
OSC
OSC
OSC
(2)
2:
3:
2: Analog levels on any pin defined as a
Configuring Analog Port Pins
(T
The RC source has a typical T
4 s.
For device frequencies above 1 MHz, the
device must be in Sleep mode for the
entire conversion or the A/D accuracy may
be out of specification.
Maximum conversion speeds are
achieved at the bolded device frequencies.
AD
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured
converted.
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
)
000
100
001
101
010
110
011
T
FREQUENCIES
AD
OH
vs. DEVICE OPERATING
or V
input
OL
Frequency (MHz)
22.86
45.71
11.43
2.86
5.71
Maximum Device
) will be converted.
48
1
(1)
will
DS39964B-page 375
be
AD
accurately
time of
2.5
1
10
20
40
48
5
(1)
(3)
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