PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 436
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 436 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
27.6
A unique feature on board the CTMU module is its
ability to generate system clock, independent output
pulses based on an external capacitor value. This is
accomplished using the internal comparator voltage
reference module, Comparator 2 input pin and an
external capacitor. The pulse is output onto the CTPLS
pin. To enable this mode, set the TGEN bit.
See Figure 27-4 for an example circuit. C
chosen by the user to determine the output pulse width
on CTPLS. The pulse width is calculated by
T = (C
source measurement step (Section 27.3.1 “Current
Source Calibration”) and V is the internal reference
voltage (CV
FIGURE 27-4:
27.7
27.7.1
When the device enters any Sleep mode, the CTMU
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not
measurements may return erroneous values.
27.7.2
The behavior of the CTMU in Idle mode is determined
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. In this
DS39964B-page 436
terminate
PULSE
Creating a Delay with the CTMU
Module
Operation During Sleep/Idle
Modes
/I)*V, where I is known from the current
REF
SLEEP MODE AND DEEP SLEEP
MODES
IDLE MODE
).
correctly.
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
C
CTED1
C2INB
PULSE
Capacitance
and
PULSE
EDG1
time
Preliminary
CV
is
Current Source
REF
Comparator
PIC18F47J53
CTMU
C2
An example use of this feature is for interfacing with
variable capacitive-based sensors, such as a humidity
sensor. As the humidity varies, the pulse width output
on CTPLS will vary. The CTPLS output pin can be
connected to an input capture pin and the varying pulse
width is measured to determine the humidity in the
application.
Follow these steps to use this feature:
1.
2.
3.
4.
5.
case, if the module is performing an operation when
Idle mode is invoked, the results will be similar to those
with Sleep mode.
27.8
Upon Reset, all registers of the CTMU are cleared. This
leaves the CTMU module disabled; its current source is
turned off and all configuration options return to their
default settings. The module needs to be re-initialized
following any Reset.
If the CTMU is in the process of taking a measurement at
the time of Reset, the measurement will be lost. A partial
charge may exist on the circuit that was being measured,
and should be properly discharged before the CTMU
makes subsequent attempts to make a measurement.
The circuit is discharged by setting and then clearing the
IDISSEN bit (CTMUCONH<1>) while the A/D Converter
is connected to the appropriate channel.
Set the CPOL bit (CMxCON<5>).
Initialize the comparator voltage reference.
Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
Set EDG1STAT.
When C
reference trip point, an output pulse is generated
on CTPLS.
Effects of a Reset on CTMU
PULSE
charges to the value of the voltage
CTPLS
2010 Microchip Technology Inc.
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