PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 212
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 212 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
FIGURE 13-1:
DS39964B-page 212
Note 1:
SOSCGO
T1OSCEN
T3OSCEN
T5OSCEN
Comparator 2
Output
Output
T1G
From Timer2
Match PR2
Comparator 1
Output
Output
T1GSS<1:0>
2:
3:
T1OSO/T1CKI
ST buffer is high-speed type when using T1CKI.
Timer1 register increments on rising edge.
Synchronization does not operate while in Sleep.
T1OSCEN
T1GPOL
T1CKI
T1OSI
Set Flag bit
TMR1IF on
Overflow
TIMER1 BLOCK DIAGRAM
01
11
00
10
TMR1ON
T1GTM
T1OSC
TMR1H
EN
OUT
TMR1
(1)
T1G_IN
(2)
D
R
CK
TMR1L
Q
Q
1
0
Preliminary
TMR1CS<1:0>
0
1
T1GGO/T1DONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
OSC
EN
/4
D
Single Pulse
Acq. Control
10
01
00
T1CLK
T1GSPM
T1CKPS<1:0>
T1SYNC
Prescaler
1, 2, 4, 8
TMR1ON
0
1
2
0
1
Internal
F
OSC
Clock
T1GVAL
TMR1GE
/2
2010 Microchip Technology Inc.
Q1
Synchronized
Synchronize
Interrupt
Clock Input
D
EN
Sleep Input
det
det
Q
(3)
Set
TMR1GIF
T1GCON
Data Bus
RD
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