PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 413
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 413 of 586
- Download datasheet (6Mb)
24.7
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.
TABLE 24-3:
2010 Microchip Technology Inc.
INTCON
PIR2
PIR5
PIE2
PIE5
IPR2
IPR5
CMxCON
CVRCON
CMSTAT
ANCON0
ANCON1
TRISA
Legend:
Name
Comparator Operation During
Sleep
— = unimplemented, read as ‘0’. Shaded cells are not related to comparator operation.
PCFG7
GIE/GIEH
OSCFIF
OSCFIE
OSCFIP
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
CVREN
VBGEN
TRISA7
Bit 7
CON
end:)
—
—
—
—
(Leg
PCFG6
PEIE/GIEL
CVROE
TRISA6
CM2IF
CM2IE
CM2IP
Bit 6
COE
end:)
—
—
—
—
—
(Leg-
PCFG5
TMR0IE
TRISA5
CM1IF
CM3IF
CM1IE
CM3IE
CM1IP
CM3IP
CPOL
CVRR
gend:)
Bit 5
—
—
Preliminary
(Le
EVPOL1
PCFG12
TMR8IE
TMR8IP
TMR8IF
CVRSS
PCFG4
INT0IE
USBIE
USBIP
USBIF
Bit 4
—
—
PIC18F47J53 FAMILY
24.8
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
EVPOL0
PCFG11
TMR6IE
TMR6IP
TMR6IF
BCL1IE
BCL1IP
TRISA3
BCL1IF
PCFG3
CVR3
RBIE
Bit 3
Effects of a Reset
—
PCFG10
TMR0IF
TMR5IF
HLVDIE
TMR5IE
HLVDIP
TMR5IP
HLVDIF
TRISA2
COUT3
PCFG2
CREF
CVR2
Bit 2
TMR5GIF
TMR5GIE
TMR5GIP
TMR3IF
TMR3IE
TMR3IP
TRISA1
COUT2
PCFG1
PCFG9
INT0IF
CCH1
CVR1
Bit 1
DS39964B-page 413
TMR1GIE
TMR1GIP
TMR1GIF
CCP2IE
CCP2IP
CCP2IF
TRISA0
COUT1
PCFG8
PCFG0
CCH0
CVR0
RBIF
Bit 0
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