PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 226
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 226 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
15.3
Timer3/5 can be configured for 16-bit reads and writes
(see
(TxCON<1>) is set, the address for TMRxH is mapped to
a buffer register for the high byte of Timer3/5. A read from
TMRxL will load the contents of the high byte of Timer3/5
into the Timerx High Byte Buffer register. This provides
users with the ability to accurately read all 16 bits of
Timer3/5 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer3/5 must also take place
through the TMRxH Buffer register. The Timer3/5 high
byte is updated with the contents of TMRxH when a write
occurs to TMRxL. This allows users to write all 16 bits to
both the high and low bytes of Timer3/5 at once.
The high byte of Timer3/5 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timerx High Byte Buffer register.
Writes to TMRxH do not clear the Timer3/5 prescaler.
The prescaler is only cleared on writes to TMRxL.
15.4
The Timer1 internal oscillator may be used as the clock
source for Timer3/5. The Timer1 oscillator is enabled
by setting the T1OSCEN (T1CON<3>) bit. To use it as
the Timer3/5 clock source, the TMRxCS bits must also
be set. As previously noted, this also configures
Timer3/5 to increment on every rising edge of the
oscillator source.
The Timer1 oscillator is described in Section 13.0
“Timer1 Module”.
FIGURE 15-2:
DS39964B-page 226
Figure 15.3). When the RD16 control bit
TMRxGE
Timer3/5
Timer3/5 16-Bit Read/Write Mode
Using the Timer1 Oscillator as the
Timer3/5 Clock Source
TxGPOL
TxGVAL
TxG_IN
TxCKI
TIMER3/5 GATE COUNT ENABLE MODE
N
Preliminary
N + 1
15.5
Timer3/5 can be configured to count freely or the count
can be enabled and disabled using the Timer3/5 gate
circuitry. This is also referred to as the Timer3/5 gate
count enable.
The Timer3/5 gate can also be driven by multiple
selectable sources.
15.5.1
The Timerx Gate Enable mode is enabled by setting
the TMRxGE bit (TxGCON<7>). The polarity of the
Timerx Gate Enable mode is configured using the
TxGPOL bit (TxGCON<6>).
When Timerx Gate Enable mode is enabled, Timer3/5
will increment on the rising edge of the Timer3/5 clock
source. When Timerx Gate Enable mode is disabled,
no incrementing will occur and Timer3/5 will hold the
current count. See Figure 15-2 for timing details.
TABLE 15-1:
† The clock on which TMR3/5 is running. For more
TxCLK
information, see TxCLK in Figure 15-1.
(†)
Timer3/5 Gates
N + 2
TIMER3/5 GATE COUNT ENABLE
(TxGCON<6>)
TxGPOL
TIMER3/5 GATE ENABLE
SELECTIONS
0
0
1
1
2010 Microchip Technology Inc.
N + 3
TxG
Pin
0
1
0
1
Counts
Holds Count
Holds Count
Counts
N + 4
Operation
Timerx
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