HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 13

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
4.3.10 Notes on Using
Cache Enhanced Mode
(SH7750R Only)
4.4.1 Configuration
• LRU (SH7750R only)
5.3.2 Exception
Handling Vector
Addresses
5.5.3 Exception
Requests and BL Bit
5.6.1 Resets
(1) Power-On Reset
(2) Manual Reset
Page
125 to
127
130
151
158
159
160
Revision (See Manual for Details)
Newly added
Description amended
• LRU (SH7750R only)
Description amended
The reset vector address is fixed at H'A000 0000. General
exception and interrupt vector addresses are determined by
adding the offset for the specific event to the vector base
address, which is set by software in the vector base register
(VBR).
Description amended
When the BL bit in SR is 0, general exception and interrupts are
accepted.
When the BL bit in SR is 1 and a general exception other than a
user break is generated, the CPU's internal registers and the
registers of the other modules are set to their states following a
manual reset, and the CPU branches to the same address as in
a reset (H'A000 0000).
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
...
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
...
SR.IMASK = B'1111;
In a 2-way set-associative cache, up to 2 items of data can
be registered in the cache at each entry address. When an
entry is registered, the LRU bit indicates which of the 2 ways
it is to be registered in. The LRU bit is a single bit of each
entry, and its value is controlled by hardware.
Rev.7.00 Oct. 10, 2008 Page xi of lxxxiv
REJ09B0366-0700