HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 860

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev.7.00 Oct. 10, 2008 Page 774 of 1074
REJ09B0366-0700
No
Framing error occurrence
Overrun error handling
framing error handling
in SCFSR2 set to 1?
in SCFDR2 = H'10?
Read receive FIFO
PER or FER bit
Bits 7 to 0
Last data?
+
Yes
Yes
No
Figure 16.14 Overrun Error Flag
No
Yes
Normal error handling
Error handling
Flow chart:
When flaming error (SCFSR.ER=1) is occurred, bit7 to
bit0 should be read out from SCFDR2. If bit7 to bit0
equals H'10, contents of the receive FIFO should be
read. When the data received last is not accompanied
with flaming error (SCFSR2.FER=0) both overrun error
handling and flaming error handling shoud be
conducted.

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