HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 925

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3.3
The interrupt-priority-level setting register 00 (INTPRI00) sets the priority levels (levels 15−0) for
the on-chip peripheral module interrupts. INTPRI00 is a 32-bit readable/writable register. It is
initialized to H'00000000 by a reset, but is not initialized when the device enters standby mode.
Initial value:
Initial value:
Table 19.7 shows the correspondence between interrupt request sources and the bits in INTPRI00.
Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register
Register
Interrupt-
priority-level
setting
register 00
Note: As shown in the table above, levels for all eight on-chip peripheral modules are assigned in
R/W:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Bit:
a single register. The interrupt priority level for the interrupt source that corresponds to each
set of four bits is set as a value from H'F (1111) to H'0 (0000). The setting H'F selects
interrupt priority level 15, which is the highest, and H'0 selects level 0, which means that
interrupt requests from that source are masked.
Reserved bits are always read as 0. When writing, only 0s should be written to these bits.
Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)
31 to 28
Reserved
31
15
R
0
0
30
14
R
0
0
27 to 24
Reserved
29
13
R
0
0
28
12
R
0
0
23 to 20
Reserved
27
11
R
0
0
26
10
R
0
0
19 to 16
Reserved
25
R
0
9
0
24
R
0
8
0
Bit
Rev.7.00 Oct. 10, 2008 Page 839 of 1074
23
15 to 12
TMU ch4 TMU ch3 Reserved
R
R
0
7
0
Section 19 Interrupt Controller (INTC)
22
R
R
0
6
0
11 to 8
21
R
R
0
5
0
20
R
R
0
4
0
7 to 4
19
R
R
0
3
0
REJ09B0366-0700
18
R
R
0
2
0
3 to 0
Reserved
17
R
R
0
1
0
16
R
R
0
0
0