HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 946

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 20 User Break Controller (UBC)
Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31–
0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or
manual reset.
Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be
used in the channel B break conditions.
20.2.10 Break Data Mask Register B (BDMRB)
Legend:
Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which
bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on
reset or manual reset.
Rev.7.00 Oct. 10, 2008 Page 860 of 1074
REJ09B0366-0700
Initial value:
Initial value:
Initial value:
Initial value:
*: Undefined
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8
BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0
R/W
R/W
R/W
R/W
31
23
15
7
*
*
*
*
R/W
R/W
R/W
R/W
30
22
14
6
*
*
*
*
R/W
R/W
R/W
R/W
29
21
13
5
*
*
*
*
R/W
R/W
R/W
R/W
28
20
12
*
*
*
4
*
R/W
R/W
R/W
R/W
27
19
11
3
*
*
*
*
R/W
R/W
R/W
R/W
26
18
10
2
*
*
*
*
R/W
R/W
R/W
R/W
25
17
*
*
9
*
1
*
R/W
R/W
R/W
R/W
24
16
8
0
*
*
*
*