HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 29

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
16.1.3 Pin
Configuration
Table 16.1 SCIF Pins
16.2.9 FIFO Control
Register (SCFCR2)
Bits 5 and 4—Transmit
FIFO Data Number
Trigger (TTRG1,
TTRG0):
16.2.11 Serial Port
Register (SCSPTR2)
17.1 Overview
17.1.3 Pin
Configuration
Table 17.1 Smart Card
Interface Pins
Page
728
747
750, 751 Description amended
775
777
Revision (See Manual for Details)
Note amended
Note: After a power-on reset, these pins function as mode input
Description amended
Initial value:
Bit 3—Reserved: This bit is always read as 0, and should only
be written with 0.
Bit 2—Reserved: The value of this bit is undefined when read.
The write value should always be 0.
Description amended
The serial communication interface (SCI) supports a subset of
the ISO/IEC 7816-3 (identification cards) standard as an
extended function.
Note added
Note: The serial clock pin and transmit data pin function as
• SH7750
Bit 5: TTRG1
0
1
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
• SH7750S/SH7750R
Bit 5: TTRG1
0
1
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
R/W:
Bit:
pins MD1, MD2 and MD8. These pins can function as
serial pins by setting the SCIF operation with the TE, RE,
and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2.
These pins are made to function as serial pins by
performing SCIF operation settings with the TE, RE, and
CKE1 bits in SCSCR2 and the MCE bit in SCFCR2.
Break state transmission and detection can be set in the
SCIF's SCSPTR2 register.
mode input pins MD0 and MD7 after a power-on reset
RTSIO
R/W
0
7
1
1
1
0
1
Bit 4: TTRG0
0
0
Bit 4: TTRG0
0
RTSDT
R/W
—
6
Rev.7.00 Oct. 10, 2008 Page xxvii of lxxxiv
CTSIO
R/W
5
0
Transmit Trigger Number
7 (9)
3 (13)
1 (15)
0 (16)
Transmit Trigger Number
8 (8)
4 (12)
2 (14)
1 (15)
CTSDT
R/W
—
4
—
R
3
0
—
—
R
2
REJ09B0366-0700
SPB2IO SPB2DT
R/W
1
0
(Initial value)
(Initial value)
R/W
—
0