HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 924

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Section 19 Interrupt Controller (INTC)
Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or
detected immediately while the SR.BL bit is set to 1.
Bit 9: NMIB
0
1
Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information
Bit 8—NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt
request signal to the NMI pin is detected.
Bit 8: NMIE
0
1
Bit 7—IRL Pin Mode (IRLM): Specifies whether pins IRL3–IRL0 are to be used as level-
encoded interrupt requests or as four independent interrupt requests.
Bit 7: IRLM
0
1
Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written
with 0.
Rev.7.00 Oct. 10, 2008 Page 838 of 1074
REJ09B0366-0700
2. This bit is cleared automatically by NMI acceptance.
will be lost, and so must be saved beforehand.
Description
NMI interrupt requests held pending while SR.BL bit is set to 1
NMI interrupt requests detected while SR.BL bit is set to 1
Description
Interrupt request detected on falling edge of NMI input
Interrupt request detected on rising edge of NMI input
Description
IRL pins used as level-encoded interrupt requests
IRL pins used as four independent interrupt requests (level-sense IRQ
mode)
(Initial value)
(Initial value)
(Initial value)

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