HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 61

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3 Register Descriptions ........................................................................................................ 835
19.4 INTC Operation ................................................................................................................ 843
19.5 Interrupt Response Time ................................................................................................... 846
19.6 Usage Notes ...................................................................................................................... 847
Section 20 User Break Controller (UBC)
20.1 Overview........................................................................................................................... 851
20.2 Register Descriptions ........................................................................................................ 854
20.3 Operation........................................................................................................................... 864
19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ............................................... 835
19.3.2 Interrupt Control Register (ICR).......................................................................... 837
19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)........ 839
19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only).............................. 840
19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) ............................... 841
19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) .............. 842
19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00
19.4.1 Interrupt Operation Sequence .............................................................................. 843
19.4.2 Multiple Interrupts ............................................................................................... 845
19.4.3 Interrupt Masking with MAI Bit .......................................................................... 845
19.6.1 NMI Interrupts (SH7750 and SH7750S Only)..................................................... 847
20.1.1 Features................................................................................................................ 851
20.1.2 Block Diagram ..................................................................................................... 852
20.2.1 Access to UBC Control Registers ........................................................................ 854
20.2.2 Break Address Register A (BARA) ..................................................................... 855
20.2.3 Break ASID Register A (BASRA)....................................................................... 856
20.2.4 Break Address Mask Register A (BAMRA)........................................................ 856
20.2.5 Break Bus Cycle Register A (BBRA).................................................................. 857
20.2.6 Break Address Register B (BARB)...................................................................... 859
20.2.7 Break ASID Register B (BASRB) ....................................................................... 859
20.2.8 Break Address Mask Register B (BAMRB) ........................................................ 859
20.2.9 Break Data Register B (BDRB) ........................................................................... 859
20.2.10 Break Data Mask Register B (BDMRB).............................................................. 860
20.2.11 Break Bus Cycle Register B (BBRB) .................................................................. 861
20.2.12 Break Control Register (BRCR) .......................................................................... 861
20.3.1 Explanation of Terms Relating to Accesses......................................................... 864
20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 864
20.3.3 User Break Operation Sequence .......................................................................... 865
20.3.4 Instruction Access Cycle Break ........................................................................... 866
20.3.5 Operand Access Cycle Break............................................................................... 867
(SH7750R Only) .................................................................................................. 842
..................................................................... 851
Rev.7.00 Oct. 10, 2008 Page lix of lxxxiv
REJ09B0366-0700