LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 109

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Note 1: These pins are outputs in mode PPFD2, inputs in mode PPFD1.
FDC on Parallel Port Pin
The “floppy on the parallel port” pin function, FDC_PP, is muxed onto GP23. This pin function can be
used to switch the parallel port pins between the FDC and the parallel port. The FDC_PP pin can
generate a PME and an SMI by enabling GP23 in the appropriate PME and SMI enable registers (bit 5
of PME_EN2 and bit 4 of SMI_EN2 – see the Runtime Registers section). This pin generates an SMI
and PME on both a low-to-high and a high-to-low edge.
The pin function for GP23 and the polarity of GP23 is selected through GPIO Polarity Register 2.
When the FDC_PP function is selected, the pin must also be selected as an input via bit 3 of the GPIO
Direction Register 2.
If the Floppy_PP bits, CR21 bits[1:0] = 01 or 10, and the FDC_PP function is selected on GP23, then
the default functionality (non-inverted polarity) for this pin is as follows: when the pin is low, the parallel
port pins are used for a floppy disk controller; when the pin is high, the parallel port pins are used for a
parallel port. The polarity bit controls the state of the pin.
If the Floppy_PP bits, CR21 bits[1:0]=00 then the pin is not used to switch the parallel port pins
between the FDC and the parallel port, even if the FDC_PP function is selected on GP23. See the
Configuration section for register description.
Note: When the floppy is selected on the parallel port, the parallel port IRQ, SMI and the parallel port
DRQ will not come out of the part.
CONNECTOR
PIN #
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
TQFP/STQFP
CHIP PIN #
83
68
69
70
71
72
73
74
75
80
79
78
77
82
81
66
67
Table 43 – FDC Parallel Port Pins
SPP MODE
nSTROBE
nERROR
nSLCTIN
BUSY
nACK
SLCT
nALF
nINIT
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE
109
DIRECTION
PIN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
FDC MODE
nDSKCHG
DRVDEN0
nWDATA
nWGATE
nRDATA
(nMTR0)
nHDSEL
nINDEX
(nDS0)
nMTR1
nSTEP
nTRK0
nDS1
nWP
nDIR
-
-
DIRECTION
I/(O) Note1
I/(O) Note1
PIN
O
O
O
O
O
O
O
O
I
I
I
I
I
-
-