LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 16

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Super I/O Registers
The address map, shown below in Table 1,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, serial and parallel
ports, runtime register block and configuration
register
configuration registers. Some addresses are
used to access more than one register.
block
Note 1: Refer to the configuration register descriptions for setting the base address.
Base+(0-5) and +(7)
Base+(0-7)
Base1+(0-7)
Base2+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Base + (0-F)
Base + (0-1)
can
be
ADDRESS
moved
Table 1 - Super I/O Block Addresses
FUNCTIONAL DESCRIPTION
via
the
Serial Port Com 1
Serial Port Com 2
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
Runtime Registers
Configuration
Floppy Disk
16
BLOCK NAME
Host Processor Interface (LPC)
The host processor communicates with the
LPC47N227 through a series of read/write
registers via the LPC interface.
addresses for these registers are shown in Table
1. Register access is accomplished through I/O
cycles or DMA transfers. All registers are 8 bits
wide.
IR Support
FIR and CIR
NOTES
The port