LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 29

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Main Status Register (MSR)
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main
Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive
data via the Data Register. It should be read before each byte transferring to or from the data register
except in DMA mode. No delay is required when reading the MSR after a data transfer.
BIT 0 - 1 DRV x BUSY
These bits are set to 1s when a drive is in the seek portion of a command, including implied and
overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has
been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek,
Recalibrate commands), this bit is returned to a 0 after the last command byte.
BIT 5 NON-DMA
This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a
command. This is for polled data transfers and helps differentiate between the data transfer phase and
the reading of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write
is required.
DT1
RQM
0
1
0
1
7
DT0
0
0
1
1
DIO
6
Table 10 – Default Precompensation Delays
DRVDEN1 (1)
DRATE0
DRATE0
DRATE0
DRATE1
NON
DMA
DATA RATE
5
500 Kbps
300 Kbps
250 Kbps
Table 9 – DRVDEN Mapping0
2 Mbps
1 Mbps
BUSY
CMD
4
DRVDEN0 (1)
29
nDENSEL
DENSEL
DRATE1
DRATE0
Reserved Reserved
PRECOMPENSATIO
3
N DELAYS
41.67 ns
20.8 ns
125 ns
125 ns
125 ns
4/2/1 MB 3.5"
2/1 MB 5.25" FDDS
2/1.6/1 MB 3.5" (3-MODE)
PS/2
2
DRIVE TYPE
BUSY
DRV1
1
BUSY
DRV0
0