LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 134

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

NAME/DEFAULT
SMI_EN1
Default = 0x00
SMI_EN2
Default = 0x00
GP1
Default = 0x00
GP2
Default = 0x00
on VTR POR
on VTR POR
on VTR POR
on VTR POR
REGISTER
OFFSET
(R/W)
(R/W)
R/W
R/W
0A
0B
0C
0D
SMI Enable Register 1
This register is used to enable the different interrupt
sources onto the internal group nSMI signal.
1=Enable
0=Disable
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
SMI Enable Register 2
This register is used to enable the different interrupt
sources onto the internal group nSMI signal, and the
internal group nSMI signal onto the nIO_SMI GPI/O pin
or the serial IRQ stream on IRQ2.
1=Enable
0=Disable
Bit[0] EN_PINT
Bit[1] EN_U2INT
Bit[2] EN_U1INT
Bit[3] EN_FINT
Bit[4] GP23
Bit[5] GP24
Bit[6] EN_SMI_S (Enable group nSMI signal onto serial
IRQ2)
Bit[7] EN_SMI (Enable group nSMI signal onto nIO_SMI
pin)
General Purpose I/O Data Register 1
Bit[0]GP10
Bit[1]GP11
Bit[2]GP12
Bit[3]GP13
Bit[4]GP14
Bit[5]GP15
Bit[6]GP16
Bit[7]GP17
General Purpose I/O Data Register 2
Bit[0]GP20
Bit[1]GP21
Bit[2]GP22
Bit[3]GP23
Bit[4]GP24
Bit[7:5]Reserved
134
DESCRIPTION