LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 30

no-image

LPC47N227TQFP

Manufacturer Part Number
LPC47N227TQFP
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47N227TQFP

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC47N227TQFP
Manufacturer:
RFT
Quantity:
386
Part Number:
LPC47N227TQFP
Manufacturer:
SMSC
Quantity:
1 000
Part Number:
LPC47N227TQFP
Manufacturer:
SMSC
Quantity:
20 000
BIT 7 RQM
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
Data Register (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data and result status are transferred between the host
processor and the floppy disk controller through the Data Register.
Data transfers are governed by the RQM and DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT
hardware compatibility. The default values can be changed through the Configure command (enable full
FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger
DMA latency without causing a disk error. Table 11 gives several examples of the delays with a FIFO.
The data is based upon the following formula:
At the start of a command, the FIFO action is always disabled and command parameters are sent based
upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of
any data to ensure that invalid data is not transferred.
An overrun or underrun will terminate the current command and the transfer of data. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove
the remaining data so that the result phase may be entered.
Threshold
# x
DATA
RATE
1
FIFO THRESHOLD
FIFO THRESHOLD
EXAMPLES
EXAMPLES
x 8 - 1.5 #s =
15 bytes
15 bytes
2 bytes
8 bytes
2 bytes
8 bytes
1 byte
1 byte
DELAY
Table 11 – FIFO Service Delay
1 x 4 #s - 1.5 #s = 2.5 #s
2 x 4 #s - 1.5 #s = 6.5 #s
8 x 4 #s - 1.5 #s = 30.5 #s
15 x 4 #s - 1.5 #s = 58.5 #s
1 x 8 #s - 1.5 #s = 6.5 #s
2 x 8 #s - 1.5 #s = 14.5 #s
8 x 8 #s - 1.5 #s = 62.5 #s
15 x 8 #s - 1.5 #s = 118.5 #s
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
30
2 Mbps DATA RATE
1 Mbps DATA RATE

Related parts for LPC47N227TQFP