LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 122

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Each GPIO port has a 1-bit data register. GPIOs are controlled by GPIO control registers located in
the Configuration section. The data register for each GPIO port is represented as a bit in one of the 8-
bit GPIO DATA Registers, GP1 to GP4. The bits in these registers reflect the value of the associated
GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value
written to the bit goes to the GPIO pin. Latched on read and write. The GPIO data registers are
located in the Runtime Register block; see the Runtime Registers section. The GPIO ports with their
alternate functions and configuration state register addresses are listed in Table 49.
Note 1: The GPIO Data Registers are located at the offset shown from the RUNTIME REGISTERS
BLOCK address.
/QFP
NO.
N/A
N/A
N/A
PIN
48
49
50
51
52
54
55
56
57
58
59
64
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
6
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Reserved
Reserved
Reserved
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
FUNCTION
DEFAULT
Table 49 – General Purpose I/O Port Assignments
nIO_SMI
IRQIN1
IRQIN2
FDC_PP
ALTERNATE
FUNCTION
122
REGISTER
DATA
GP1
GP2
GP3
GP4
1
REGISTER BIT
DATA
NO.
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
REGISTER
OFFSET
(HEX)
0C
0D
0E
0F