LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 37

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid
Command" condition.
Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-
DMA mode as indicated in the Specify command.
After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending
on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold>
is defined as the number of bytes available to the FDC when service is requested from the host and
ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to
15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster
servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until
empty (full), then the transfer request goes inactive. The host must be very responsive to the service
request. This is the desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after
a service request, but results in more frequent service requests.
Non-DMA Mode - Transfers from the FIFO to the Host
The interrupt and RQM bit in the Main Status Register are activated when the FIFO contains (16-
<threshold>) bytes or the last bytes of a full sector have been placed in the FIFO. The interrupt can be
used for interrupt-driven systems, and RQM can be used for polled systems. The host must respond to
the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of
the FIFO. The FDC will deactivate the interrupt and RQM bit when the FIFO becomes empty.
Non-DMA Mode - Transfers from the Host to the FIFO
The interrupt and RQM bit in the Main Status Register are activated upon entering the execution phase of
data transfer commands. The host must respond to the request by writing data into the FIFO. The
interrupt and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has
<threshold> bytes remaining in the FIFO. The FDC enters the result phase after the last byte is taken by
the FDC from the FIFO (i.e. FIFO empty condition).
DMA Mode - Transfers from the FIFO to the Host
The FDC generates a DMA request cycle when the FIFO contains (16 - <threshold>) bytes, or the last
byte of a full sector transfer has been placed in the FIFO. The DMA controller responds to the request by
reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by
generating the proper sync for the data transfer.
DMA Mode - Transfers from the Host to the FIFO.
The FDC generates a DMA request cycle when entering the execution phase of the data transfer
commands. The DMA controller responds by placing data in the FIFO. The DMA request remains active
until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has <threshold> bytes
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