LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 153

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR14 can only be accessed in the configuration state and after the CSR has been initialized to 14H.
CR14 shadows the bits in the write-only FDC run-time DSR register.
CR15
CR15 can only be accessed in the configuration state and after the CSR has been initialized to 15H.
CR15 shadows the bits in the write-only UART1 run-time FCR register.
BIT NO.
BIT NO.
2-4
0,1
4,5
6,7
5
6
7
0
1
2
3
XMIT FIFO Reset Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and
PRECOMP 0-2
RCVR Trigger
SOFTRESET
PWRDOWN
FIFO Enable
RCVR FIFO
DMA Mode
Type: R/W
BIT NAME
BIT NAME
Data Rate
Select 0-1
Reserved
Reserved
Type: R
Select
Reset
UART1 FCR Shadow Register
These bits select the data rate of the floppy controller.
These three bits select the value of write precompensation that will
be applied to the WDATA output signal.
Read Only. A read returns 0.
A logic "1" written to this bit will put the floppy controller into manual
low power mode.
A logic "0" written to this bit resets the floppy disk controller. This
bit is self clearing.
Setting this bit to a logic "1" enables both the XMIT and RCVR
FIFOs
Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and
resets its counter logic to 0. This bit is self clearing.
resets its counter logic to 0. This bit is self-clearing.
Writing to this bit has no effect on the operation of the UART.
Read Only. A read returns 0.
These bits are used to set the trigger level for the RCVR FIFO
interrupt.
BIT7
DSR Shadow Register
0
0
1
1
Table 75 – CR14
Table 76 - CR15
153
BIT6
0
1
0
1
DESCRIPTION
DESCRIPTION
RCVR FIFO Trigger Level (BYTES)
Default: N/A
Default: N/A
14
1
4
8