LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 21

no-image

LPC47N227TQFP

Manufacturer Part Number
LPC47N227TQFP
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47N227TQFP

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC47N227TQFP
Manufacturer:
RFT
Quantity:
386
Part Number:
LPC47N227TQFP
Manufacturer:
SMSC
Quantity:
1 000
Part Number:
LPC47N227TQFP
Manufacturer:
SMSC
Quantity:
20 000
The Floppy Disk Controller (FDC) provides the
interface between a host microprocessor and the
floppy disk drives.
functions of the Formatter/Controller, Digital Data
Separator, Write Precompensation and Data Rate
Selection logic for an IBM XT/AT compatible FDC.
The true CMOS 765B core guarantees 100% IBM
PC XT/AT compatibility in addition to providing
data overflow and underflow protection.
The FDC is compatible to the 82077AA using
SMSC's proprietary floppy disk controller core.
The LPC47N227 supports one floppy disk drive
directly through the FDC interface pins and two
Status Register A (SRA)
Address 3F0 READ ONLY
This register is read-only and monitors the state
of the internal interrupt signal and several disk
ADDRESS
PRIMARY
3F0
3F1
3F2
3F3
3F4
3F4
3F5
3F6
3F7
3F7
The FDC integrates the
Table 2 – Status, Data and Control Registers
SECONDARY
(Shown with base addresses of 3F0 and 370)
ADDRESS
370
371
372
373
374
374
375
376
377
377
FLOPPY DISK CONTROLLER
R/W
R/W
R/W
R/W
W
W
R
R
R
R
21
floppy disk drives via the FDC interface on the
parallel port pins. It can also be configured to
support one drive on the FDC interface pins and
one drive on the parallel port pins.
FDC Internal Registers
The Floppy Disk Controller contains eight internal
registers that facilitate the interfacing between the
host microprocessor and the disk drive. Table 2
shows the addresses required to access these
registers. Registers other than the ones shown
are not supported. The rest of the description
assumes that the primary addresses have been
selected.
interface pins in PS/2 and Model 30 modes. The
SRA can be accessed at any time when in PS/2
mode. In the PC/AT mode the data bus pins D0
- D7 are held in a high impedance state for a
read of address 3F0.
Status Register A (SRA)
Status Register B (SRB)
Digital Output Register (DOR)
Tape Drive Register (TDR)
Main Status Register (MSR)
Data Rate Select Register (DSR)
Data (FIFO)
Reserved
Digital Input Register (DIR)
Configuration Control Register (CCR)
REGISTER

Related parts for LPC47N227TQFP