LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 8
LPC47N227TQFP
Manufacturer Part Number
LPC47N227TQFP
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LPC47N227TQFP.pdf
(200 pages)
Specifications of LPC47N227TQFP
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC47N227TQFP
Manufacturer:
RFT
Quantity:
386
Part Number:
LPC47N227TQFP
Manufacturer:
SMSC
Quantity:
20 000
- Current page: 8 of 200
- Download datasheet (658Kb)
TQFP/STQFP
PIN #
100
89
90
92
91
94
95
96
61
62
63
Data Terminal
Ready 1
Data Terminal
Ready 2
Ring
Indicator 1
(Note 8)
Ring
Indicator 2
(Note 8)
Data Carrier
Detect 1
Data Carrier
Detect 2
Receive Data 2
Transmit
Data 2
IR Receive
IR Transmit
IR Mode/
IR Receive 3
NAME
nDTR1
nDTR2
nRI1
nRI2
nDCD1
nDCD2
RXD2
TXD2
IRRX2
IRTX2
IRMODE/
IRRX3
SYMBOL
PARALLEL PORT INTERFACE (NOTE 3)
INFRARED INTERFACE
FUNCTION
TYPE PER
BUFFER
O12
O12
O6/
O6
O6
IS
IS
IS
I
I
I
I
1
8
Active low Data Terminal Ready outputs for the
serial port.
modem that the UART is ready to establish data
communication
programmed by writing to bit 0 of Modem Control
Register (MCR). The hardware reset will reset the
nDTR signal to inactive mode (high).
forced inactive during loop mode operation.
Active low Ring Indicator inputs for the serial port.
Handshake signal which notifies the UART that the
telephone ring signal is detected by the modem.
The CPU can monitor the status of nRI signal by
reading bit 6 of Modem Status Register (MSR). A
nRI signal state change from low to high after the
last MSR read will set MSR bit 2 to a 1. If bit 3 of
Interrupt Enable Register is set, the interrupt is
generated when nRI changes state.
Note: Bit 6 of MSR is the complement of nRI.
Active low Data Carrier Detect inputs for the serial
port. Handshake signal which notifies the UART
that carrier signal is detected by the modem. The
CPU can monitor the status of nDCD signal by
reading bit 7 of Modem Status Register (MSR). A
nDCD signal state change from low to high after
the last MSR read will set MSR bit 3 to a 1. If bit 3
of Interrupt Enable Register is set, the interrupt is
generated when nDCD changes state.
Note: Bit 7 of MSR is the complement of nDCD.
Receiver serial data input for port 2. IR Receive
Data.
Transmit serial data output for port 2. IR transmit
data.
IR Receive.
IR Transmit.
IR mode.
IR Receive 3.
Handshake output signal notifies
DESCRIPTION
link.
This
signal
can
nDTR is
be
Related parts for LPC47N227TQFP
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
USB CHIP
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
ULTRA FAST USB 2.0 MULTI-SLOT FLASH MEDI
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet: