LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 129

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Runtime Registers Block Summary
The runtime registers are located at the address programmed in the Runtime Register Block Base
Address configuration register located in CR30. The part performs 16-bit address qualification on the
Runtime Register Base Address (bits[11:0] are decoded and bits[15:12] must be zero). The runtime
register block may be located within the range 0x0100-0x0FFF on 16-byte boundaries. Decodes are
disabled if the Runtime Register Base Address is located below 0x100. These registers are powered
by VTR.
Note: Hard Reset: nPCI_RESET pin asserted.
Note: Reserved bits return 0 on read.
Note 1: The parallel port interrupt defaults to 1 when the parallel port power bit is cleared. When the
OFFSET (hex)
REGISTER
parallel port is activated, PINT follows the nACK input.
0C
0D
0A
0B
0E
0F
00
01
02
03
04
05
06
07
08
09
Table 52 - Runtime Register Block Summary
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RUNTIME REGISTERS
RESET
HARD
Note 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
129
VCC POR
Note 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VTR POR
Note 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
PME_STS
PME_EN
PME_STS1
PME_STS2
PME_STS3
PME_EN1
PME_EN2
PME_EN3
SMI_STS1
SMI_STS2
SMI_EN1
SMI_EN2
GP1
GP2
GP3
GP4
REGISTER