LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 133

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

NAME/DEFAULT
PME_EN3
Default = 0x00
SMI_STS1
Default = 0x00
SMI_STS2
Default = 0x01
Bit 0 is set to ‘1’
on VCC POR,
VTR POR and
HARD RESET
on VTR POR
on VTR POR
on VTR POR
REGISTER
OFFSET
(R/W)
(R/W)
(R/W)
07
08
09
PME Wake Enable Register 3
This register is used to enable individual LPC47N227
PME wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake
source is active (“1”), if the source asserts a wake
event so that the associated status bit is “1” and the
PME_En bit is “1”, the source will assert the nIO_PME
signal.
When the PME Wake Enable register bit for a wake
source is inactive (“0”), the PME Wake Status register
will indicate the state of the wake source but will not
assert the nIO_PME signal.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP34
Bit[5] GP35
Bit[6] GP36
Bit[7] GP37
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
SMI Status Register 1
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
SMI Status Register 2
This register is used to read the status of the SMI inputs.
The bits[3:0] must be cleared at their source. Bits[5:4]
are cleared on a write of ‘1’.
Bit[0] PINT.
when the parallel port activate bit is cleared. When the
parallel port is activated, PINT follows the nACK input.
Bit[1] U2INT
Bit[2] U1INT
Bit[3] FINT
Bit[4] GP23
Bit[5] GP24
Bit[7:6] Reserved
133
The parallel port interrupt defaults to ‘1’
DESCRIPTION