LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 161

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR29
CR29 can only be accessed in the configuration state and after the CSR has been initialized to 29H.
CR29 controls the HPMODE bit and is used to select the IRQ mapping (bits 0 - 3) for the IRQIN1 pin.
Refer to IRQ encoding for CR27 (Table 90). Any unselected IRQ output (registers CR27 - CR29) is in
tristate.
CR2A
CR2A can only be accessed in the configuration state and after the CSR has been initialized to 2AH.
CR2A is used to select the IRQ mapping (bits 0 - 3) for the IRQIN2 pin. Refer to IRQ encoding for
CR27 (Table 90). Any unselected IRQ output (registers CR27 - CR29) is in tristate.
BIT NO.
BIT NO.
It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ
number. Potential damage to chip may result. Note: Z = Don’t Care.
0-3
3:0
7:4
4
5
7
OUT2 bit
UART1
0
1
1
0
0
1
1
1
1
UART1
IRQIN1
HPMODE
RESERVED
SIRQ_CLKRUN_E
N
Output State
Type: R/W
Type: R/W
BIT NAME
BIT NAME
UART1 IRQ
de-asserted
de-asserted
de-asserted
Reserved
IRQIN2
asserted
asserted
asserted
Z
Z
Z
Table 92 – UART Interrupt Operation
IRQIN1/HPMODE/SIRQ_CLKRUN_En
Selects the IRQ for IRQIN1.
FIGURE 2 – INFRARED INTERFACE BLOCK DIAGRAM
Not Writeable, Reads Return “0”
Serial IRQ and CLKRUN enable bit. 0 = Disable 1 = Enable
(default)
Selects the IRQ for IRQIN2.
Read Only. A read returns 0.
OUT2 bit
UART2
0
1
0
0
0
1
1
1
1
1
1
Table 94 – CR2A
Table 93 – CR29
UART2
IRQIN2
Select IRMODE (default)
Select IRRX3
161
Output State
UART2 IRQ
de-asserted
de-asserted
de-asserted
asserted
asserted
asserted
Z
Z
Z
DESCRIPTION
DESCRIPTION
Default: 0x80 on VCC POR
Default: 0x00 on VCC POR
Pin State
See
UART1
Z
Z
Z
1
0
1
1
0
0
IRQ PINS
Pin State
UART2
Z
Z
Z
1
0
1
0
1
0