LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 14

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

3.3 Volt Operation / 5 Volt Tolerance
The LPC47N227 is a 3.3 Volt part. It is intended
solely for 3.3V applications. Non-LPC bus pins
are 5V tolerant; that is, the input voltage is 5.5V
max, and the I/O buffer output pads are
backdrive protected.
The LPC interface pins are 3.3 V only. These
signals meet PCI DC specifications for 3.3V
signaling. These pins are:
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The input voltage for all other pins is 5.5V max.
These pins include all non-LPC Bus pins and the
following pins:
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Power Functionality
The LPC47N227 has two power planes: VCC
and VTR.
VCC Power
The LPC47N227 is a 3.3 Volt part. The VCC
supply is 3.3 Volts (nominal).
Operational
Maximum Current Values subsection.
VTR Support
The LPC47N227 requires a trickle supply (V
to provide sleep current for the programmable
wake-up events in the PME interface when V
is removed.
(nominal).
Section.
required depends on the functions that are used
in the part.
subsection and the Maximum Current Values
subsection. If the LPC47N227 is not intended to
provide wake-up capabilities on standby current,
LAD[3:0]
nLFRAME
nLDRQ
nLPCPD
nPCI_RESET
PCI_CLK
SER_IRQ
nCLKRUN
nIO_PME
The maximum VTR current that is
See the Operational Description
Description
See Trickle Power Functionality
The VTR supply is 3.3 Volts
Section
and
See the
the
TR
CC
)
14
generates a V
initialize these components.
Note: If V
wake-up events when V
be at its full minimum potential at least 10 #s
before V
and V
difference between the two supplies must not
exceed 500mV.
Internal PWRGOOD
An
included to minimize the effects of pin-state
uncertainty in the host interface as V
and off. When the internal PWRGOOD signal is
“1” (active), V
LPC47N227 host interface is active. When the
internal PWRGOOD signal is “0” (inactive), V
$ 2.3V (nominal), and the LPC47N227 host
interface is inactive; that is, LPC bus reads and
writes will not be decoded.
The LPC47N227 device pins nIO_PME, nRI1,
nRI2, and most GPIOs (as input) are part of the
PME interface and remain active when the
internal PWRGOOD signal has gone inactive,
provided V
Functionality section.
Trickle Power Functionality
When the LPC47N227 is running under VTR
only, the PME wakeup events are active and (if
enabled) able to assert the nIO_PME pin active
low. The following lists the wakeup events:
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The following requirements apply to all I/O pins
that are specified to be 5 volt tolerant.
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TR
UART 1 Ring Indicator
UART 2 Ring Indicator
GPIOs for wakeup. See below.
compatible are powered by VCC.
VTR power (VCC=0), these pins may only
be configured as inputs. These pins have
input buffers into the wakeup logic that are
powered by VTR.
internal PWRGOOD logical control is
CC
CC
buffers
TR
TR
begins a power-on cycle. When V
are fully powered, the potential
is to be used for programmable
is powered.
CC
TR
> 2.3V (nominal), and the
that
Power-on-Reset signal to
CC
are
is removed, V
See Trickle Power
CC
wake-up
CC
cycles on
TR
TR
Under
event
must
CC
TR