LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 95

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle.
Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable
transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for
low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers
permits the use of adaptive signal timing Peer-to-peer capability.
Vocabulary
The following terms are used in this document:
assert:
forward: Host to Peripheral communication.
reverse: Peripheral to Host communication
Pword:
always 8 bits.
1
0
These terms may be considered synonymous:
PeriphClk, nAck
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
SIGNAL
EPP
For correct EPP read cycles, PCD is required to be a low.
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a
"false" state.
A high level.
A low level.
A port word; equal in size to the width of the LPC interface. For this implementation, PWord is
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
nAddress
Strobe
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Status
Error
EPP NAME
TYPE
I/O
O
O
O
O
Table 36 - EPP Pin Descriptions
I
I
I
I
I
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low.
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is
ready for the next transfer.
This signal is active low. It is used to denote data read or write
operation.
is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
This signal is active low. When driven active, the EPP device
95
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
EPP DESCRIPTION
It is driven inactive as a positive