PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 125

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.7.3.6
Figure 70
Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable
(MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER,
MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE prevents the occurrence of MDR status, including when the first byte of a packet is
received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is
generated only for the first byte of a receive packet. When both MRE and MRC are
active, MDR is always generated and all received MONITOR bytes - marked by a 1-to-0
transition in MX bit - are stored (additionally, an active MRC enables the control of the
MR handshake bit according to the MONITOR channel protocol).
Figure 70
Data Sheet
shows the MONITOR interrupt structure of the IPAC-X. The MONITOR Data
MONITOR Interrupt Logic
TRAN
MASK
WOV
MOS
ICD
ST
CIC
Interrupt
ICA
ICB
MONITOR Interrupt Structure
TRAN
ISTA
WOV
MOS
ICD
ST
CIC
ICA
ICB
125
Description of Functional Blocks
MOCR
MRE
MIE
PSB/PSF 21150
MOSR
MER
MAB
MDR
MDA
2003-01-30
IPAC-X