PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 268

PSB21150FV14XT

Manufacturer Part Number
PSB21150FV14XT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB21150FV14XT

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
R
RAB bit
RAC bit
RACI bit
RAH1 register
RAH2 register
RAL1 register
RAL2 register
RBC11-8 bits
RBC7-0 bits
RBCHB register
RBCHD register
RBCLB register
RBCLD register
RCRC bit
RDO bit
Receive PLL
Register description
RES_xxx bits
Reset generation
Reset source selection
Reset timing
RFBS bits
RFIFOB register
RFIFOD register
RFO bit
RIC bit
RINF bits
RLP bit
RMC bit
RME bit
RPF bit
RPLL_ADJ bit
RRES bit
RSS2/1 bits
RSTAB register
RSTAD register
S
S/G bit
S/T-Interface
Data Sheet
Circuitry
199
136, 187
193
175, 232
185, 242
179, 236
175, 232
185, 242
175, 232
178, 234
177, 233
178, 234
194
180, 237
180, 237
227
183, 240
259
73
50
184, 241
230
241
242
238
240
192
240
242
183
185
241
184
244
174
44
64
165
44
268
SA1/0 bits
SAP1 register
SAP2 register
S-bus priority mechanism
SCI - serial control interface
SCI interface timing
SDS
SDS_CONF register
SDS2/1_BCL bits
SDSx_CR registers
Serial data strobe
SGD bit
SGP bit
Shifting data
SLIP bit
Software reset
SPU bit
SQC bit
SQR1-4 bits
SQR21-24 bits
SQR31-34 bits
SQR41-44 bits
SQR51-54 bits
SQRR1 register
SQRR2 register
SQRR3 register
SQW bit
SQX1-4 bits
SQX21-24
SQX31-34 bits
SQX41-44 bits
SQX51-54 bits
SQXR1 register
SQXR2 register
SQXR3 register
114
Coding
Delay compensation
External protection circuitry
Multiframe synchronization
Multiframing
Receiver characteristics
Transceiver enable/disable
Transmitter characteristics
216
193
193
194
199
199
185
198
197
196
103
182
183
45
198
198
198
197
197
198
198
197
198
198
196
197
198
52
219
114
215
254
219
PSB/PSF 21150
54
131
36
2003-01-30
66
IPAC-X
63
62
56
67
64

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