PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 79

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.5.1.3
Command
Activation Request with
priority class 8
Activation Request with
priority class 10
Activation Request Loop ARL
Deactivation Indication
Reset
Timing
Test mode SSP
Test mode SCP
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
Data Sheet
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is permanently issued.
C/I Codes (TE, LT-T)
Abbr. Code Remark
AR8
AR10 1001 Activation requested by the IPAC-X, D-
DI
RES
TIM
SSP
SCP
1000 Activation requested by the IPAC-X, D-
1010 Activation requested for the internal or
1111 Deactivation Indication.
0001 Reset of the layer-1 state machine.
0000 Layer-2 device requires clocks to be
0010 One AMI-coded pulse transmitted in each
0011 AMI-coded pulses transmitted continuously,
channel priority set to 8 (see note).
channel priority set to 10 (see note).
external Loop A (see note).
For a non transparent internal loop bit
DIS_TX of register TR_CONF2 has to be set
to ’1’ additionally.
activated.
frame, resulting in a frequency of the
fundamental mode of 2 kHz.
resulting in a frequency of the fundamental
mode of 96 kHz.
79
Description of Functional Blocks
PSB/PSF 21150
2003-01-30
IPAC-X