PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 210

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

SDSx_CR ENS_
4.4.10
Value after reset: 00
Register
SDS1_CR
SDS2_CR
This register is used to select position and length of the strobe signals. The length can
be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
For general information please refer to
ENS_TSS ... Enable Serial Data Strobe of timeslot TSS
ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TSS+1
0: The serial data strobe signal SDSx is inactive during TSS, TSS+1
1: The serial data strobe signal SDSx is active during TSS, TSS+1
ENS_TSS+3 ... Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
0: The serial data strobe signal SDSx is inactive during the D-channel (bit7, 6) of TSS+3
1: The serial data strobe signal SDSx is active during the D-channel (bit7, 6) of TSS+3
TSS ... Timeslot Selection
Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which
SDSx is active high or provides a strobed BCL clock output (see SDS_CONF.SDS1/
2_BCL). The data strobe signal allows standard data devices to access a programmable
channel.
Data Sheet
7
SDSx_CR - Control Register Serial Data Strobe x
TSS
TSS+1
ENS_
H
TSS+3
ENS_
Register Address
55
56
H
H
Chapter 3.7.2
210
TSS
and
Detailed Register Description
Chapter
Value after Reset
00
00
H
H
0
3.7.2.2.
PSB/PSF 21150
2003-01-30
IPAC-X
RD/WR
(55-56)