PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 174

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MASKD
STARD
If an XDU interrupt occurs the transmit FIFO is locked until the XDU interrupt is read by
the host (interrupt cannot be read if masked in MASKD).
4.1.4
Value after reset: FF
Each interrupt source in the ISTAD register can selectively be masked by setting the
corresponding bit in MASKD to ’1’. Masked interrupt status bits are not indicated when
ISTAD is read. Instead, they remain internally stored and pending until the mask bit is
reset to ’0’.
4.1.5
Value after reset: 40
XDOV ... Transmit Data Overflow
More than 16 or 32 bytes (according to selected block size) have been written to the
XFIFOD, i.e. data has been overwritten.
XFW ... Transmit FIFO Write Enable
Data can be written to the XFIFOD. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
RACI ... Receiver Active Indication
The D-channel HDLC receiver is active when RACI = ’1’. This bit may be polled. The
RACI bit is set active after a begin flag has been received and is reset after receiving an
abort sequence.
Data Sheet
7
7
XDOV XFW
MASKD - Mask Register D-Channel
STARD - Status Register D-Channel
RME
RPF
H
H
RFO
0
XPR
0
174
RACI
XMR
XDU
0
Detailed Register Description
XACI
1
0
0
PSB/PSF 21150
1
0
2003-01-30
IPAC-X
WR (20)
RD (21)