PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 189

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

TR_
CONF1
Note: The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’.
For general information please refer to
LDD ... Level Detection Discard
0: Automatic clock generation after detection of any signal on the line in
power down state
1: No clock generation after detection of any signal on the line in power down state
Note: If an interrupt by the level detect circuitry is generated, the microcontroller has to
For general information please refer to
4.2.2
Value after reset: 0x
RPLL_ADJ ... Receive PLL Adjustment
0: DPLL tracking step is 0.5 XTAL period per S-frame
1: DPLL tracking step is 1 XTAL period per S-frame
EN_SFSC ... Enable Short FSC
0: No short FSC is generated
1: A short FSC is generated once per multi-frame (every 40th IOM frame)
x ... Undefined
The value of these bits depends on the selected mode. It is important to note that these
bits must not be overwritten to a different value when accessing this register.
Data Sheet
set this bit to ’0’ for an activation of the S/T interface.
7
TR_CONF1 - Transceiver Configuration Register 1
0
RPLL_
ADJ
H
SFSC
EN_
0
Chapter
Chapter 3.3.9
189
0
3.3.11.
x
and
Detailed Register Description
Chapter
x
0
3.7.6.
PSB/PSF 21150
x
RD/WR (31)
2003-01-30
IPAC-X