PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 188

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

TR_
CONF0
4.2
4.2.1
Value after reset: 01
DIS_TR ... Disable Transceiver
Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver
again, a transceiver reset must be issued (SRES.RES_TR=1). The transceiver must not
be reenabled by setting DIS_TR from “1” to “0”.
For general information please refer to
BUS ... Point-to-Point / Bus Selection (NT / Int. NT / LT-S mode only)
0: Adaptive Timing (Point-t-Point, extended passive bus).
1: Fixed Timing (Short passive bus).
EN_ICV ... Enable Illegal Code Violation
0:normal operation
1:ICV enabled. The receipt of at least one illegal code violation within one multi-frame is
indicated by the C/I indication ’1011’ (CVR) in two consecutive IOM frames.
L1SW ... Enable Layer 1 State Machine in Software
0:Layer 1 state machine of the IPAC-X is used
1:Layer 1 state machine is disabled. The functionality can be realized in software.
The commands can be written to register TR_CMD and the status can be read from
TR_STA.
For general information please refer to
EXLP ... External loop
In case the analog loopback is activated with C/I = ARL or with the LP_A bit in the
TR_CMD register the loop is a
0: internal loop next to the line pins
1: external loop which has to be closed between SR1/2 and SX1/SX2
Data Sheet
7
Transceiver Registers
TR_CONF0 - Transceiver Configuration Register 0
DIS_
TR
BUS
H
EN_
ICV
0
Chapter
Chapter
188
L1SW
3.3.10.
3.5.
0
Detailed Register Description
EXLP
0
LDD
PSB/PSF 21150
RD/WR (30)
2003-01-30
IPAC-X