PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 30

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Table 2
Pin No.
MQFP-64
TQFP-64
60
Miscellaneous
43
44
47
48
35
36
57
Data Sheet
Symbol Input (I)
AUX7
SX1
SX2
SR1
SR2
XTAL1
XTAL2
MODE0 I
IPAC-X Pin Definitions and Functions (cont’d)
Output (O)
Open Drain
(OD)
I/O (OD)
O
O
I
I
I
O
Function
INT1
This pin is programmable as general input/output.
The state of the pin can be read from (input) / written
to (output) a register.
Additionally, as input it can generate a maskable
interrupt to the host, which is either edge or level
triggered. An internal pull up resistor is connected to
this pin (open drain mode only), if push pull
characteristic is selected no pull up is available.
As output an LED can directly be connected to this
pin.
SGO
Instead of the above described function, AUX7 can
also be programmed to output the S/G bit signal
from the IOM-2 DD line.
S-Bus Transmitter Output (positive)
S-Bus Transmitter Output (negative)
S-Bus Receiver Input
S-Bus Receiver Input
Crystal 1
Connection for a crystal or used as external clock
input. 7.68 MHz clock or crystal required.
Crystal 2
Connection for a crystal. Not connected if an
external clock is supplied to XTAL1
Mode 0 Select
A LOW selects TE-mode and a HIGH selects LT-T /
LT-S mode (see MODE1/EAW).
30
Pin Configuration
PSB/PSF 21150
2003-01-30
IPAC-X