PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 136

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

2. Terminal Transmits D-Channel Data Upstream
The initial state is identical to that described in the last paragraph. When one of the
connected S-bus terminals needs to transmit in the D-channel, access is established
according to the following procedure:
• IPAC-X S-transceiver (in intelligent NT) recognizes that the D-channel on the S-bus is
• IPAC-X S-transceiver transfers S-bus D-channel data transparently through to the
For both cases described above the exchange indicates via the A/B bit (controlled by
layer 1) that D-channel transmission on this line is permitted (A/B = “1”). Data
transmission could temporarily be prohibited by the exchange when only a single
D-channel controller handles more lines (A/B = “0”, ELIC-concept).
In case the exchange prohibits D data transmission on this line the A/B bit is set to “0”
(block). For U
S-transceiver to transmit an inverted echo channel on the S-bus, thus disabling all
terminal requests, and switches S/G to A/B, which blocks the D-channel controller in the
intelligent NT.
Note: Although the IPAC-X S-transceiver operates in LT-S mode and is pinstrapped to
Figure 76
Data Sheet
active.
upstream IOM-2 bus (IOM-2 channel 0).
TE
TE
TE
IOM-2 channel 0 or 1 it will write into IOM-2 channel 2 at the S/G bit position.
Data Flow for Collision Resolution Procedure in Intelligent NT
PN
D-channel
E-channel
applications with S extension this forces the intelligent NT IPAC-X
(LT-S mode)
Layer 1
IPAC-X
D
BAC
D
S/G
A/B
D-channel controller
e.g. ICC PEB 2070
S
(TE mode timing)
136
S/G
D-channel
controller
D
D
D
D
Description of Functional Blocks
BAC
IOM
TBA
DU
DD
Masterdevice,
e.g. IEC-Q TE
transceiver
IOM-2
U
PSB/PSF 21150
21150_03
Exchange
2003-01-30
IPAC-X