PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 165

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

The address range from 40
timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver
data (TR), Monitor data (MON), HDLC/CI data (HCI) and controller access data (CDA),
serial data strobe signal (SDS), IOM interface (IOM) and synchronous transfer interrupt
(STI).
The address range from 5C
General interrupt and configuration registers are contained in the address range
60
The address range 70
controllers having an identical set of registers.
The register summaries of the IPAC-X are shown in the following tables containing the
abbreviation of the register name and the register bits, the register address, the reset
values and the register type (Read/Write). A detailed register description follows these
register summaries.
The register summaries and the description are sorted in ascending order of the register
address.
Name
RFIFOD
XFIFOD
ISTAD
MASKD
STARD
CMDRD RMC RRES
MODED MDS2 MDS1 MDS0
EXMD1
TIMR1
SAP1
Data Sheet
H
-65
H
.
D-channel HDLC, C/I-channel Handler
7
XDOV XFW
XFBS
RME
RME
6
CNT
RPF
RPF
RFBS
H
5
-8F
RFO
RFO
D-Channel Transmit FIFO
D-Channel Receive FIFO
H
H
0
0
H
SAPI1
-5B
-5F
is assigned to the two B-channel FIFOs and HDLC
4
H
H
XPR
XPR
SRA XCRC RCRC
STI
pertains to the MONITOR handler.
is assigned to the IOM handler with the registers for
0
0
3
RACI
XMR
XMR
RAC DIM2 DIM1 DIM0
XTF
165
2
VALUE
XDU
XDU
0
0
1
XACI
Detailed Register Description
XME XRES
0
1
0
0
0
MHA
ITF
0
1
0
PSB/PSF 21150
ADDR R/WRES
00
00
1F
1F
20
20
21
21
22
23
24
25
H
H
H
H
H
H
H
H
H
H
H
H
-
-
2003-01-30
R/W C0
R/W 00
R/W 00
IPAC-X
W
W FF
W 00
W FC
R
R 10
R 40
H
H
H
H
H
H
H
H